From: Greg KH <gregkh@linuxfoundation.org>
To: Wu Hao <hao.wu@intel.com>
Cc: mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-api@vger.kernel.org,
linux-doc@vger.kernel.org, atull@kernel.org,
Ananda Ravuri <ananda.ravuri@intel.com>,
Xu Yilun <yilun.xu@intel.com>
Subject: Re: [PATCH v3 04/12] fpga: dfl: afu: add AFU state related sysfs interfaces
Date: Wed, 24 Jul 2019 11:41:10 +0200 [thread overview]
Message-ID: <20190724094110.GD29532@kroah.com> (raw)
In-Reply-To: <1563857495-26692-5-git-send-email-hao.wu@intel.com>
On Tue, Jul 23, 2019 at 12:51:27PM +0800, Wu Hao wrote:
> This patch introduces more sysfs interfaces for Accelerated
> Function Unit (AFU). These interfaces allow users to read
> current AFU Power State (APx), read / clear AFU Power (APx)
> events which are sticky to identify transient APx state,
> and manage AFU's LTR (latency tolerance reporting).
>
> Signed-off-by: Ananda Ravuri <ananda.ravuri@intel.com>
> Signed-off-by: Xu Yilun <yilun.xu@intel.com>
> Signed-off-by: Wu Hao <hao.wu@intel.com>
> Acked-by: Alan Tull <atull@kernel.org>
> Signed-off-by: Moritz Fischer <mdf@kernel.org>
> ---
> v2: rebased, and remove DRV/MODULE_VERSION modifications
> v3: update kernel version and date in sysfs doc
> ---
> Documentation/ABI/testing/sysfs-platform-dfl-port | 30 +++++
> drivers/fpga/dfl-afu-main.c | 137 ++++++++++++++++++++++
> drivers/fpga/dfl.h | 11 ++
> 3 files changed, 178 insertions(+)
>
> diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-port b/Documentation/ABI/testing/sysfs-platform-dfl-port
> index 6a92dda..5961fb2 100644
> --- a/Documentation/ABI/testing/sysfs-platform-dfl-port
> +++ b/Documentation/ABI/testing/sysfs-platform-dfl-port
> @@ -14,3 +14,33 @@ Description: Read-only. User can program different PR bitstreams to FPGA
> Accelerator Function Unit (AFU) for different functions. It
> returns uuid which could be used to identify which PR bitstream
> is programmed in this AFU.
> +
> +What: /sys/bus/platform/devices/dfl-port.0/power_state
> +Date: July 2019
> +KernelVersion: 5.4
> +Contact: Wu Hao <hao.wu@intel.com>
> +Description: Read-only. It reports the APx (AFU Power) state, different APx
> + means different throttling level. When reading this file, it
> + returns "0" - Normal / "1" - AP1 / "2" - AP2 / "6" - AP6.
> +
> +What: /sys/bus/platform/devices/dfl-port.0/ap1_event
> +Date: July 2019
> +KernelVersion: 5.4
> +Contact: Wu Hao <hao.wu@intel.com>
> +Description: Read-write. Read or set 1 to clear AP1 (AFU Power State 1)
> + event. It's used to indicate transient AP1 state.
So reading the value changes the state of the system? That's almost
always never a good idea.
Force userspace to write the value to change something. Otherwise all
libraries that use sysfs will be accidentally changing the state of your
system without you ever knowing it.
> +
> +What: /sys/bus/platform/devices/dfl-port.0/ap2_event
> +Date: July 2019
> +KernelVersion: 5.4
> +Contact: Wu Hao <hao.wu@intel.com>
> +Description: Read-write. Read or set 1 to clear AP2 (AFU Power State 2)
> + event. It's used to indicate transient AP2 state.
> +
> +What: /sys/bus/platform/devices/dfl-port.0/ltr
> +Date: July 2019
> +KernelVersion: 5.4
> +Contact: Wu Hao <hao.wu@intel.com>
> +Description: Read-write. Read and set AFU latency tolerance reporting value.
> + Set ltr to 1 if the AFU can tolerate latency >= 40us or set it
> + to 0 if it is latency sensitive.
> diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
> index 68b4d08..cb3f73e 100644
> --- a/drivers/fpga/dfl-afu-main.c
> +++ b/drivers/fpga/dfl-afu-main.c
> @@ -141,8 +141,145 @@ static int port_get_id(struct platform_device *pdev)
> }
> static DEVICE_ATTR_RO(id);
>
> +static ssize_t
> +ltr_show(struct device *dev, struct device_attribute *attr, char *buf)
> +{
> + struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
> + void __iomem *base;
> + u64 v;
> +
> + base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
> +
> + mutex_lock(&pdata->lock);
> + v = readq(base + PORT_HDR_CTRL);
> + mutex_unlock(&pdata->lock);
Why do you need a lock to call readq()? What are you protecting here?
> +
> + return sprintf(buf, "%x\n", (u8)FIELD_GET(PORT_CTRL_LATENCY, v));
> +}
> +
> +static ssize_t
> +ltr_store(struct device *dev, struct device_attribute *attr,
> + const char *buf, size_t count)
> +{
> + struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
> + void __iomem *base;
> + u8 ltr;
> + u64 v;
> +
> + if (kstrtou8(buf, 0, <r) || ltr > 1)
> + return -EINVAL;
Are you doing anything with this value? If not, how about just using
the sysfs boolean read function and if it is 1, then do the clearing?
Same for all other show/store functions in here.
thanks,
greg k-h
next prev parent reply other threads:[~2019-07-24 9:41 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-23 4:51 [PATCH v3 00/12] FPGA DFL updates Wu Hao
2019-07-23 4:51 ` [PATCH v3 01/12] fpga: dfl: fme: support 512bit data width PR Wu Hao
2019-07-24 9:35 ` Greg KH
2019-07-24 14:22 ` Wu Hao
2019-08-14 16:34 ` Scott Wood
2019-08-15 3:58 ` Wu Hao
2019-07-23 4:51 ` [PATCH v3 02/12] fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support Wu Hao
2019-07-24 9:33 ` Greg KH
2019-07-24 13:47 ` Wu Hao
2019-07-23 4:51 ` [PATCH v3 03/12] fpga: dfl: pci: enable SRIOV support Wu Hao
2019-07-24 9:37 ` Greg KH
2019-07-24 13:37 ` Wu Hao
2019-07-23 4:51 ` [PATCH v3 04/12] fpga: dfl: afu: add AFU state related sysfs interfaces Wu Hao
2019-07-24 9:41 ` Greg KH [this message]
2019-07-24 13:29 ` Wu Hao
2019-07-23 4:51 ` [PATCH v3 05/12] fpga: dfl: afu: add userclock " Wu Hao
2019-07-23 4:51 ` [PATCH v3 06/12] fpga: dfl: add id_table for dfl private feature driver Wu Hao
2019-07-23 4:51 ` [PATCH v3 07/12] fpga: dfl: afu: export __port_enable/disable function Wu Hao
2019-07-23 4:51 ` [PATCH v3 08/12] fpga: dfl: afu: add error reporting support Wu Hao
2019-07-23 4:51 ` [PATCH v3 09/12] fpga: dfl: afu: add STP (SignalTap) support Wu Hao
2019-07-24 10:11 ` Greg KH
2019-07-24 13:03 ` Wu Hao
2019-07-23 4:51 ` [PATCH v3 10/12] fpga: dfl: fme: add capability sysfs interfaces Wu Hao
2019-07-23 4:51 ` [PATCH v3 11/12] fpga: dfl: fme: add global error reporting support Wu Hao
2019-07-23 4:51 ` [PATCH v3 12/12] Documentation: fpga: dfl: add descriptions for virtualization and new interfaces Wu Hao
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