[PATCH v2 0/3] arm64: Brahma-B53 erratum updates

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* [PATCH v2 0/3] arm64: Brahma-B53 erratum updates
@ 2019-10-31 21:47 Florian Fainelli
  2019-10-31 21:47 ` [PATCH v2 1/3] arm64: apply ARM64_ERRATUM_845719 workaround for Brahma-B53 core Florian Fainelli
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Florian Fainelli @ 2019-10-31 21:47 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Florian Fainelli, Catalin Marinas, Will Deacon, Jonathan Corbet,
	Suzuki K Poulose, Mark Rutland, Vladimir Murzin, Thomas Gleixner,
	Doug Berger, Hanjun Guo, Qian Cai, Zhang Lei, Marc Zyngier,
	Jeremy Linton, Andre Przywara, open list:DOCUMENTATION, open list

Hi Will,

This patch series enable the Brahma-B53 CPU to be matched for the
ARM64_ERRATUM_845719 and ARM64_ERRATUM_843419 and while we are it, also
whitelists it for SSB and spectre v2.

The silicon-errata.rst document is updated accordingly, we unfortunately
do not have internal numbers tracking those errata.

Doug Berger (1):
  arm64: apply ARM64_ERRATUM_845719 workaround for Brahma-B53 core

Florian Fainelli (2):
  arm64: Brahma-B53 is SSB and spectre v2 safe
  arm64: apply ARM64_ERRATUM_843419 workaround for Brahma-B53 core

 Documentation/arm64/silicon-errata.rst |  5 ++++
 arch/arm64/include/asm/cputype.h       |  2 ++
 arch/arm64/kernel/cpu_errata.c         | 38 ++++++++++++++++++++++----
 3 files changed, 40 insertions(+), 5 deletions(-)

-- 
2.17.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH v2 1/3] arm64: apply ARM64_ERRATUM_845719 workaround for Brahma-B53 core
  2019-10-31 21:47 [PATCH v2 0/3] arm64: Brahma-B53 erratum updates Florian Fainelli
@ 2019-10-31 21:47 ` Florian Fainelli
  2019-10-31 21:47 ` [PATCH v2 2/3] arm64: Brahma-B53 is SSB and spectre v2 safe Florian Fainelli
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Florian Fainelli @ 2019-10-31 21:47 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Doug Berger, Florian Fainelli, Catalin Marinas, Will Deacon,
	Jonathan Corbet, Suzuki K Poulose, Mark Rutland, Vladimir Murzin,
	Thomas Gleixner, Hanjun Guo, Qian Cai, Zhang Lei, Marc Zyngier,
	Jeremy Linton, Andre Przywara, open list:DOCUMENTATION, open list

From: Doug Berger <opendmb@gmail.com>

The Broadcom Brahma-B53 core is susceptible to the issue described by
ARM64_ERRATUM_845719 so this commit enables the workaround to be applied
when executing on that core.

Since there are now multiple entries to match, we must convert the
existing ARM64_ERRATUM_845719 into an erratum list.

Signed-off-by: Doug Berger <opendmb@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 Documentation/arm64/silicon-errata.rst |  3 +++
 arch/arm64/include/asm/cputype.h       |  2 ++
 arch/arm64/kernel/cpu_errata.c         | 13 +++++++++++--
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index ab7ed2fd072f..57757c73ead1 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -91,6 +91,9 @@ stable kernels.
 | ARM            | MMU-500         | #841119,826419  | N/A                         |
 +----------------+-----------------+-----------------+-----------------------------+
 +----------------+-----------------+-----------------+-----------------------------+
+| Broadcom       | Brahma-B53      | N/A             | ARM64_ERRATUM_845719        |
++----------------+-----------------+-----------------+-----------------------------+
++----------------+-----------------+-----------------+-----------------------------+
 | Cavium         | ThunderX ITS    | #22375,24313    | CAVIUM_ERRATUM_22375        |
 +----------------+-----------------+-----------------+-----------------------------+
 | Cavium         | ThunderX ITS    | #23144          | CAVIUM_ERRATUM_23144        |
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index b1454d117cd2..aca07c2f6e6e 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -79,6 +79,7 @@
 #define CAVIUM_CPU_PART_THUNDERX_83XX	0x0A3
 #define CAVIUM_CPU_PART_THUNDERX2	0x0AF
 
+#define BRCM_CPU_PART_BRAHMA_B53	0x100
 #define BRCM_CPU_PART_VULCAN		0x516
 
 #define QCOM_CPU_PART_FALKOR_V1		0x800
@@ -105,6 +106,7 @@
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
 #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
+#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
 #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
 #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 6c3b10a41bd8..c065dd48d661 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -737,6 +737,16 @@ static const struct midr_range erratum_1418040_list[] = {
 };
 #endif
 
+#ifdef CONFIG_ARM64_ERRATUM_845719
+static const struct midr_range erratum_845719_list[] = {
+	/* Cortex-A53 r0p[01234] */
+	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
+	/* Brahma-B53 r0p[0] */
+	MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
+	{},
+};
+#endif
+
 const struct arm64_cpu_capabilities arm64_errata[] = {
 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
 	{
@@ -777,10 +787,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
 #endif
 #ifdef CONFIG_ARM64_ERRATUM_845719
 	{
-	/* Cortex-A53 r0p[01234] */
 		.desc = "ARM erratum 845719",
 		.capability = ARM64_WORKAROUND_845719,
-		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
+		ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
 	},
 #endif
 #ifdef CONFIG_CAVIUM_ERRATUM_23154
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH v2 2/3] arm64: Brahma-B53 is SSB and spectre v2 safe
  2019-10-31 21:47 [PATCH v2 0/3] arm64: Brahma-B53 erratum updates Florian Fainelli
  2019-10-31 21:47 ` [PATCH v2 1/3] arm64: apply ARM64_ERRATUM_845719 workaround for Brahma-B53 core Florian Fainelli
@ 2019-10-31 21:47 ` Florian Fainelli
  2019-10-31 21:47 ` [PATCH v2 3/3] arm64: apply ARM64_ERRATUM_843419 workaround for Brahma-B53 core Florian Fainelli
  2019-11-01 12:01 ` [PATCH v2 0/3] arm64: Brahma-B53 erratum updates Will Deacon
  3 siblings, 0 replies; 5+ messages in thread
From: Florian Fainelli @ 2019-10-31 21:47 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Florian Fainelli, Catalin Marinas, Will Deacon, Jonathan Corbet,
	Suzuki K Poulose, Mark Rutland, Vladimir Murzin, Thomas Gleixner,
	Doug Berger, Hanjun Guo, Qian Cai, Zhang Lei, Marc Zyngier,
	Jeremy Linton, Andre Przywara, open list:DOCUMENTATION, open list

Add the Brahma-B53 CPU (all versions) to the whitelists of CPUs for the
SSB and spectre v2 mitigations.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/arm64/kernel/cpu_errata.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index c065dd48d661..9b1ba1f489ac 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -489,6 +489,7 @@ static const struct midr_range arm64_ssb_cpus[] = {
 	MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 	MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 	MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
+	MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
 	{},
 };
 
@@ -573,6 +574,7 @@ static const struct midr_range spectre_v2_safe_list[] = {
 	MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 	MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 	MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
+	MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
 	{ /* sentinel */ }
 };
 
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH v2 3/3] arm64: apply ARM64_ERRATUM_843419 workaround for Brahma-B53 core
  2019-10-31 21:47 [PATCH v2 0/3] arm64: Brahma-B53 erratum updates Florian Fainelli
  2019-10-31 21:47 ` [PATCH v2 1/3] arm64: apply ARM64_ERRATUM_845719 workaround for Brahma-B53 core Florian Fainelli
  2019-10-31 21:47 ` [PATCH v2 2/3] arm64: Brahma-B53 is SSB and spectre v2 safe Florian Fainelli
@ 2019-10-31 21:47 ` Florian Fainelli
  2019-11-01 12:01 ` [PATCH v2 0/3] arm64: Brahma-B53 erratum updates Will Deacon
  3 siblings, 0 replies; 5+ messages in thread
From: Florian Fainelli @ 2019-10-31 21:47 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Florian Fainelli, Catalin Marinas, Will Deacon, Jonathan Corbet,
	Suzuki K Poulose, Mark Rutland, Vladimir Murzin, Thomas Gleixner,
	Doug Berger, Hanjun Guo, Qian Cai, Zhang Lei, Marc Zyngier,
	Jeremy Linton, Andre Przywara, open list:DOCUMENTATION, open list

The Broadcom Brahma-B53 core is susceptible to the issue described by
ARM64_ERRATUM_843419 so this commit enables the workaround to be applied
when executing on that core.

Since there are now multiple entries to match, we must convert the
existing ARM64_ERRATUM_843419 into an erratum list and use
cpucap_multi_entry_cap_matches to match our entries.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 Documentation/arm64/silicon-errata.rst |  2 ++
 arch/arm64/kernel/cpu_errata.c         | 23 ++++++++++++++++++++---
 2 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index 57757c73ead1..7b9afffac3a7 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -93,6 +93,8 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | Broadcom       | Brahma-B53      | N/A             | ARM64_ERRATUM_845719        |
 +----------------+-----------------+-----------------+-----------------------------+
+| Broadcom       | Brahma-B53      | N/A             | ARM64_ERRATUM_843419        |
++----------------+-----------------+-----------------+-----------------------------+
 +----------------+-----------------+-----------------+-----------------------------+
 | Cavium         | ThunderX ITS    | #22375,24313    | CAVIUM_ERRATUM_22375        |
 +----------------+-----------------+-----------------+-----------------------------+
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 9b1ba1f489ac..64e0f7810fba 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -749,6 +749,23 @@ static const struct midr_range erratum_845719_list[] = {
 };
 #endif
 
+#ifdef CONFIG_ARM64_ERRATUM_843419
+static const struct arm64_cpu_capabilities erratum_843419_list[] = {
+	{
+		/* Cortex-A53 r0p[01234] */
+		.matches = is_affected_midr_range,
+		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
+		MIDR_FIXED(0x4, BIT(8)),
+	},
+	{
+		/* Brahma-B53 r0p[0] */
+		.matches = is_affected_midr_range,
+		ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
+	},
+	{},
+};
+#endif
+
 const struct arm64_cpu_capabilities arm64_errata[] = {
 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
 	{
@@ -780,11 +797,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
 #endif
 #ifdef CONFIG_ARM64_ERRATUM_843419
 	{
-	/* Cortex-A53 r0p[01234] */
 		.desc = "ARM erratum 843419",
 		.capability = ARM64_WORKAROUND_843419,
-		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
-		MIDR_FIXED(0x4, BIT(8)),
+		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
+		.matches = cpucap_multi_entry_cap_matches,
+		.match_list = erratum_843419_list,
 	},
 #endif
 #ifdef CONFIG_ARM64_ERRATUM_845719
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* Re: [PATCH v2 0/3] arm64: Brahma-B53 erratum updates
  2019-10-31 21:47 [PATCH v2 0/3] arm64: Brahma-B53 erratum updates Florian Fainelli
                   ` (2 preceding siblings ...)
  2019-10-31 21:47 ` [PATCH v2 3/3] arm64: apply ARM64_ERRATUM_843419 workaround for Brahma-B53 core Florian Fainelli
@ 2019-11-01 12:01 ` Will Deacon
  3 siblings, 0 replies; 5+ messages in thread
From: Will Deacon @ 2019-11-01 12:01 UTC (permalink / raw)
  To: Florian Fainelli
  Cc: linux-arm-kernel, Catalin Marinas, Jonathan Corbet,
	Suzuki K Poulose, Mark Rutland, Vladimir Murzin, Thomas Gleixner,
	Doug Berger, Hanjun Guo, Qian Cai, Zhang Lei, Marc Zyngier,
	Jeremy Linton, Andre Przywara, open list:DOCUMENTATION, open list

On Thu, Oct 31, 2019 at 02:47:22PM -0700, Florian Fainelli wrote:
> This patch series enable the Brahma-B53 CPU to be matched for the
> ARM64_ERRATUM_845719 and ARM64_ERRATUM_843419 and while we are it, also
> whitelists it for SSB and spectre v2.

Cheers, queued as fixes.

Will

^ permalink raw reply	[flat|nested] 5+ messages in thread

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2019-10-31 21:47 [PATCH v2 0/3] arm64: Brahma-B53 erratum updates Florian Fainelli
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2019-10-31 21:47 ` [PATCH v2 2/3] arm64: Brahma-B53 is SSB and spectre v2 safe Florian Fainelli
2019-10-31 21:47 ` [PATCH v2 3/3] arm64: apply ARM64_ERRATUM_843419 workaround for Brahma-B53 core Florian Fainelli
2019-11-01 12:01 ` [PATCH v2 0/3] arm64: Brahma-B53 erratum updates Will Deacon

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