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From: "Raj, Ashok" <ashok.raj@intel.com>
To: Sinan Kaya <okaya@kernel.org>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
	"Spassov, Stanislav" <stanspas@amazon.de>,
	"corbet@lwn.net" <corbet@lwn.net>,
	"alex.williamson@redhat.com" <alex.williamson@redhat.com>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"Wang, Wei" <wawei@amazon.de>,
	"akpm@linux-foundation.org" <akpm@linux-foundation.org>,
	"Schoenherr, Jan H." <jschoenh@amazon.de>,
	"rajatja@google.com" <rajatja@google.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
	Ashok Raj <ashok.raj@intel.com>
Subject: Re: [PATCH 1/3] PCI: Make PCIE_RESET_READY_POLL_MS configurable
Date: Thu, 27 Feb 2020 18:18:55 -0800	[thread overview]
Message-ID: <20200228021855.GA57330@otc-nc-03> (raw)
In-Reply-To: <e162efcd-70fd-3390-2452-4915af1c9171@kernel.org>

On Thu, Feb 27, 2020 at 06:44:56PM -0500, Sinan Kaya wrote:
> On 2/27/2020 4:45 PM, Bjorn Helgaas wrote:
> > The 60 second timeout came from 821cdad5c46c ("PCI: Wait up to 60
> > seconds for device to become ready after FLR") and is probably too
> > long.  We probably should pick a smaller value based on numbers from
> > the spec and make quirks for devices that needed more time.
> 
> If I remember right, there was no time mention about how long to
> wait. Spec says device should send CRS as long as it is not ready.

Not exactly.. there are some requirements to follow for rules after
a conventional reset. 

Look for "The second set of rules addresses requirements placed on the system"

i'm looking a the 5.0 spec (around page 553) :-). 

In general 1s seems good enough for most cases. For ports that support
> 5gt/s transfer speed, it says 100ms after link training completes.
I'm not sure if this means 100ms after getting a DLLSC event?

  reply	other threads:[~2020-02-28  2:18 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20200223122057.6504-1-stanspas@amazon.com>
2020-02-23 12:20 ` [PATCH 1/3] PCI: Make PCIE_RESET_READY_POLL_MS configurable Stanislav Spassov
2020-02-24 14:15   ` Bjorn Helgaas
2020-02-24 17:52     ` Spassov, Stanislav
2020-02-27 21:45       ` Bjorn Helgaas
2020-02-27 23:44         ` Sinan Kaya
2020-02-28  2:18           ` Raj, Ashok [this message]
2020-03-02 16:39             ` Sinan Kaya
2020-03-02 17:37               ` Raj, Ashok
2020-03-02 18:30                 ` Sinan Kaya

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