Re: [PATCH RFC 3/3] Documentation: x86: microcode: add description for metadata file

[Borislav Petkov <bp@alien8.de>]

On Mon, Apr 27, 2020 at 10:27:59AM +0300, Mihai Carabas wrote:
> +Here is an example of content for the metadata file::
> +   m + 0x00000122
> +   m - 0x00000120

That's not enough. Imagine a blob adds the MSR and a subsequent blob
adds *another* bit in that MSR. You need to be able express that.

IOW, I think it would be easier if each line describes exactly *one*
software-visible change brought by the microcode.

Also, what is the use case to say that you're adding a new MSR?

This would require to patch all the code that *potentially* might use
that MSR, to be able to handle a *change* in that MSR or it appearing
all of a sudden. Yuck.

I mean, an easy way to handle it is to say, "Hmm, nope, won't load that
ucode."

> +   c + 0x00000007 0x00 0x00000000 0x021cbfbb 0x00000000 0x00000000
> +   c - 0x00000007 0x00 0x00000000 0x021cbfbb 0x00000000 0x00000000

I don't think this'll work with the vendors as depending on the
configuration, CPUID on the different platforms could be different.

And then you might gonna have to specify CPUID for this particular
{family,model,stepping, ... } tuple which identifies the platform
uniquely so the c-line is insufficient.

IOW, I think it would be easier to be able to specify one CPUID bit per
line of being added/removed so that the post-load callback can handle
this properly. And this specification needs to be complete: i.e.

"I'm adding this CPUID bit for this family,model,stepping configurations
under this and that conditions".

And that needs to be describable by the "language" of the metadata.

So think of actual examples and then try to represent them with this
format.

But all of this is moot if you don't get a vendor buy-in into this. IOW,
microcode vendors need to agree to this format and adhere to the format
when allowing microcode to late-load.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette