From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3A50C433E0 for ; Thu, 4 Feb 2021 03:38:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A444B64F5D for ; Thu, 4 Feb 2021 03:38:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234618AbhBDDhq (ORCPT ); Wed, 3 Feb 2021 22:37:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234485AbhBDDh2 (ORCPT ); Wed, 3 Feb 2021 22:37:28 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2546C061573 for ; Wed, 3 Feb 2021 19:36:47 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id g15so972120pjd.2 for ; Wed, 03 Feb 2021 19:36:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=z/pPsjpNFL1AOj/V+7CEjl7TXj+nEWHQjNVxoyWjhMA=; b=JpENPKrAHYNY/1bfV8ya7o3ydolLhfwkhhlfiq8Y3ndGsBDNZyyREvA3oxsFX5NrLu 4OIN/wsPWAe+9uxm8bYw9PRkGKOpaNMyy1bZxgMADjqDFDWavvkIW8pfwnbtdMYJVHiS aoa+yBHC35SfUiJyFFSbt64rikzTW9O/Pe9aifCLXGqIgqIeRGqJDDIGCS80tEyxjz9O YGQ7TOZc/0YQWMv7mv9sabhRHFo7ehY3pS8Z5iFZFdZ+ituSWgAW9m7MSMJow24O6OhV H6R2lzwkZaFSLHYN7CU1mIExLhtBG5+jJ09bmAhUjVp4LRbBEHuBFwN0pxsZtoianbJs bINQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=z/pPsjpNFL1AOj/V+7CEjl7TXj+nEWHQjNVxoyWjhMA=; b=Be0KHgcWjGQhQjGVmywX0j20mkKdykXzn4ST/eMZWI8CSD7KpqTAek/m1RK9avpCe3 pu23HIhMDwSIB1nL2SGSXO0rzJWZliACo6OUBlq2FE6Jc9WqwJxkj2Ta5q4N5GN4T2Vl zW+v8m8/uTuRTAb+NrB++Td7yJZeadLhti3Z3tiPhZH4+YbCKkmaloPLzrvASfAzY6cQ 4GsiIHXSi+baTV1nIrKwQLYvM9Jy+5QodJzOIEQHFt24S1Prj5g6HghgnMxHZb1rGT77 hz6NiNGA7aGscYHyDdSpDMaJC8wm1WjBBP2+2DID2R4DLN88VpQV2+ZsFYSm7YWcxjwR 0v/A== X-Gm-Message-State: AOAM533gFiXo/FHsKid2gXQ893wzOV9LycPxssxOgsz1vzaQ2IkM70aV crd2aYGRWuqJbRQepaSa19sr7Q== X-Google-Smtp-Source: ABdhPJzbPCh4kVIug8LRnR3bHrD8di6i9tGyckVHug4fny38LYmXqhAqJ9xCPXH7CsEth7n7+NrJew== X-Received: by 2002:a17:902:503:b029:e1:82d:bd4f with SMTP id 3-20020a1709020503b02900e1082dbd4fmr6078956plf.28.1612409807296; Wed, 03 Feb 2021 19:36:47 -0800 (PST) Received: from leoy-ThinkPad-X240s ([202.131.71.236]) by smtp.gmail.com with ESMTPSA id w13sm3936565pfc.7.2021.02.03.19.36.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 19:36:46 -0800 (PST) Date: Thu, 4 Feb 2021 11:36:39 +0800 From: Leo Yan To: Suzuki K Poulose Cc: Arnaldo Carvalho de Melo , Mathieu Poirier , Mike Leach , Jonathan Corbet , Alexander Shishkin , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Mark Rutland , Jiri Olsa , Namhyung Kim , Daniel Kiss , Denis Nikitin , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/7] coresight: etm-perf: Clarify comment on perf options Message-ID: <20210204033639.GD11059@leoy-ThinkPad-X240s> References: <20210202163842.134734-1-leo.yan@linaro.org> <20210202163842.134734-2-leo.yan@linaro.org> <071d1235-c8c4-7b3f-11ce-91c1f907ea8d@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <071d1235-c8c4-7b3f-11ce-91c1f907ea8d@arm.com> Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org Hi Suzuki, On Tue, Feb 02, 2021 at 11:00:42PM +0000, Suzuki Kuruppassery Poulose wrote: > Hi Leo > > On 2/2/21 4:38 PM, Leo Yan wrote: > > In theory, the options should be arbitrary values and are neutral for > > any ETM version; so far perf tool uses ETMv3.5/PTM ETMCR config bits > > except for register's bit definitions, also uses as options. > > > > This can introduce confusion, especially if we want to add a new option > > but the new option is not supported by ETMv3.5/PTM ETMCR. But on the > > other hand, we cannot change options since these options are generic > > CoreSight PMU ABI. > > > > For easier maintenance and avoid confusion, this patch refines the > > comment to clarify perf options, and gives out the background info for > > these bits are coming from ETMv3.5/PTM. Afterwards, we should take > > these options as general knobs, and if there have any confliction with > > ETMv3.5/PTM, should consider to define saperate macros for ETMv3.5/PTM > > ETMCR config bits. > > > > Suggested-by: Suzuki K Poulose > > Signed-off-by: Leo Yan > > The patch looks good to me. The only concern I have is, whether > we should split this patch to kernel vs tools ? As the kernel > changes go via coresight tree and the tools patch may go via > perf tree ? Yes, will split the patch. > Either way, for the patch: > > Reviewed-by: Suzuki K Poulose Thanks for review and suggestion. > > --- > > .../hwtracing/coresight/coresight-etm-perf.c | 5 ++++- > > include/linux/coresight-pmu.h | 17 ++++++++++++----- > > tools/include/linux/coresight-pmu.h | 17 ++++++++++++----- > > 3 files changed, 28 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c > > index bdc34ca449f7..465ef1aa8c82 100644 > > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c > > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c > > @@ -27,7 +27,10 @@ static bool etm_perf_up; > > static DEFINE_PER_CPU(struct perf_output_handle, ctx_handle); > > static DEFINE_PER_CPU(struct coresight_device *, csdev_src); > > -/* ETMv3.5/PTM's ETMCR is 'config' */ > > +/* > > + * The PMU formats were orignally for ETMv3.5/PTM's ETMCR 'config'; > > + * now take them as general formats and apply on all ETMs. > > + */ > > PMU_FORMAT_ATTR(cycacc, "config:" __stringify(ETM_OPT_CYCACC)); > > PMU_FORMAT_ATTR(contextid, "config:" __stringify(ETM_OPT_CTXTID)); > > PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS)); > > diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h > > index b0e35eec6499..5dc47cfdcf07 100644 > > --- a/include/linux/coresight-pmu.h > > +++ b/include/linux/coresight-pmu.h > > @@ -10,11 +10,18 @@ > > #define CORESIGHT_ETM_PMU_NAME "cs_etm" > > #define CORESIGHT_ETM_PMU_SEED 0x10 > > -/* ETMv3.5/PTM's ETMCR config bit */ > > -#define ETM_OPT_CYCACC 12 > > -#define ETM_OPT_CTXTID 14 > > -#define ETM_OPT_TS 28 > > -#define ETM_OPT_RETSTK 29 > > +/* > > + * Below are the definition of bit offsets for perf option, and works as > > + * arbitrary values for all ETM versions. > > + * > > + * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, > > + * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and > > + * directly use below macros as config bits. > > + */ > > +#define ETM_OPT_CYCACC 12 > > +#define ETM_OPT_CTXTID 14 > > +#define ETM_OPT_TS 28 > > +#define ETM_OPT_RETSTK 29 > > /* ETMv4 CONFIGR programming bits for the ETM OPTs */ > > #define ETM4_CFG_BIT_CYCACC 4 > > diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h > > index b0e35eec6499..5dc47cfdcf07 100644 > > --- a/tools/include/linux/coresight-pmu.h > > +++ b/tools/include/linux/coresight-pmu.h > > @@ -10,11 +10,18 @@ > > #define CORESIGHT_ETM_PMU_NAME "cs_etm" > > #define CORESIGHT_ETM_PMU_SEED 0x10 > > -/* ETMv3.5/PTM's ETMCR config bit */ > > -#define ETM_OPT_CYCACC 12 > > -#define ETM_OPT_CTXTID 14 > > -#define ETM_OPT_TS 28 > > -#define ETM_OPT_RETSTK 29 > > +/* > > + * Below are the definition of bit offsets for perf option, and works as > > + * arbitrary values for all ETM versions. > > + * > > + * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, > > + * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and > > + * directly use below macros as config bits. > > + */ > > +#define ETM_OPT_CYCACC 12 > > +#define ETM_OPT_CTXTID 14 > > +#define ETM_OPT_TS 28 > > +#define ETM_OPT_RETSTK 29 > > /* ETMv4 CONFIGR programming bits for the ETM OPTs */ > > #define ETM4_CFG_BIT_CYCACC 4 > > >