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[68.147.0.187]) by smtp.gmail.com with ESMTPSA id f127sm14038890pgc.48.2021.02.08.09.34.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Feb 2021 09:34:28 -0800 (PST) Date: Mon, 8 Feb 2021 10:34:26 -0700 From: Mathieu Poirier To: Leo Yan Cc: Arnaldo Carvalho de Melo , Suzuki K Poulose , Mike Leach , Jonathan Corbet , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Mark Rutland , Jiri Olsa , Namhyung Kim , Daniel Kiss , Denis Nikitin , Al Grant , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 2/8] tools headers UAPI: Update tools' copy of linux/coresight-pmu.h Message-ID: <20210208173426.GA2077938@xps15> References: <20210206150833.42120-1-leo.yan@linaro.org> <20210206150833.42120-3-leo.yan@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210206150833.42120-3-leo.yan@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On Sat, Feb 06, 2021 at 11:08:27PM +0800, Leo Yan wrote: > To get the changes in the commit: > > "coresight: etm-perf: Clarify comment on perf options". > > Signed-off-by: Leo Yan > Reviewed-by: Suzuki K Poulose Reviewed-by: Mathieu Poirier > --- > tools/include/linux/coresight-pmu.h | 17 ++++++++++++----- > 1 file changed, 12 insertions(+), 5 deletions(-) > > diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h > index b0e35eec6499..5dc47cfdcf07 100644 > --- a/tools/include/linux/coresight-pmu.h > +++ b/tools/include/linux/coresight-pmu.h > @@ -10,11 +10,18 @@ > #define CORESIGHT_ETM_PMU_NAME "cs_etm" > #define CORESIGHT_ETM_PMU_SEED 0x10 > > -/* ETMv3.5/PTM's ETMCR config bit */ > -#define ETM_OPT_CYCACC 12 > -#define ETM_OPT_CTXTID 14 > -#define ETM_OPT_TS 28 > -#define ETM_OPT_RETSTK 29 > +/* > + * Below are the definition of bit offsets for perf option, and works as > + * arbitrary values for all ETM versions. > + * > + * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, > + * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and > + * directly use below macros as config bits. > + */ > +#define ETM_OPT_CYCACC 12 > +#define ETM_OPT_CTXTID 14 > +#define ETM_OPT_TS 28 > +#define ETM_OPT_RETSTK 29 > > /* ETMv4 CONFIGR programming bits for the ETM OPTs */ > #define ETM4_CFG_BIT_CYCACC 4 > -- > 2.25.1 >