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[68.147.0.187]) by smtp.gmail.com with ESMTPSA id j10sm5817403pjs.11.2021.04.01.09.53.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 09:53:55 -0700 (PDT) Date: Thu, 1 Apr 2021 10:53:53 -0600 From: Mathieu Poirier To: Mike Leach Cc: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com, yabinc@google.com, corbet@lwn.net, leo.yan@linaro.org, alexander.shishkin@linux.intel.com, tingwei@codeaurora.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 06/10] coresight: etm-perf: Update to activate selected configuration Message-ID: <20210401165353.GB145043@xps15> References: <20210316180400.7184-1-mike.leach@linaro.org> <20210316180400.7184-7-mike.leach@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210316180400.7184-7-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On Tue, Mar 16, 2021 at 06:03:56PM +0000, Mike Leach wrote: > Add calls to activate the selected configuration as perf starts > and stops the tracing session. > > Signed-off-by: Mike Leach > Reviewed-by: Suzuki K Poulose Reviewed-by: Mathieu Poirier > --- > drivers/hwtracing/coresight/coresight-etm-perf.c | 14 +++++++++++++- > drivers/hwtracing/coresight/coresight-etm-perf.h | 2 ++ > 2 files changed, 15 insertions(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c > index 66bda452a2f4..9128f59864a8 100644 > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c > @@ -196,6 +196,10 @@ static void free_event_data(struct work_struct *work) > /* Free the sink buffers, if there are any */ > free_sink_buffer(event_data); > > + /* clear any configuration we were using */ > + if (event_data->cfg_hash) > + cscfg_deactivate_config(event_data->cfg_hash); > + > for_each_cpu(cpu, mask) { > struct list_head **ppath; > > @@ -254,7 +258,7 @@ static void etm_free_aux(void *data) > static void *etm_setup_aux(struct perf_event *event, void **pages, > int nr_pages, bool overwrite) > { > - u32 id; > + u32 id, cfg_hash; > int cpu = event->cpu; > cpumask_t *mask; > struct coresight_device *sink = NULL; > @@ -271,6 +275,14 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > sink = coresight_get_sink_by_id(id); > } > > + /* check if user wants a coresight configuration selected */ > + cfg_hash = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32); > + if (cfg_hash) { > + if (cscfg_activate_config(cfg_hash)) > + goto err; > + event_data->cfg_hash = cfg_hash; > + } > + > mask = &event_data->mask; > > /* > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h > index ba617fe2217e..468f7799ab4f 100644 > --- a/drivers/hwtracing/coresight/coresight-etm-perf.h > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h > @@ -49,12 +49,14 @@ struct etm_filters { > * @work: Handle to free allocated memory outside IRQ context. > * @mask: Hold the CPU(s) this event was set for. > * @snk_config: The sink configuration. > + * @cfg_hash: The hash id of any coresight config selected. > * @path: An array of path, each slot for one CPU. > */ > struct etm_event_data { > struct work_struct work; > cpumask_t mask; > void *snk_config; > + u32 cfg_hash; > struct list_head * __percpu *path; > }; > > -- > 2.17.1 >