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[68.147.0.187]) by smtp.gmail.com with ESMTPSA id n8sm11649402pgm.7.2021.05.10.12.28.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 12:28:32 -0700 (PDT) Date: Mon, 10 May 2021 13:28:30 -0600 From: Mathieu Poirier To: Mauro Carvalho Chehab Cc: Linux Doc Mailing List , Jonathan Corbet , Leo Yan , Mike Leach , Suzuki K Poulose , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 11/53] docs: trace: coresight: coresight-etm4x-reference.rst: avoid using UTF-8 chars Message-ID: <20210510192830.GA7232@xps15> References: <859218d35d495d5d2c2893bf8e6e087394a107a7.1620641727.git.mchehab+huawei@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <859218d35d495d5d2c2893bf8e6e087394a107a7.1620641727.git.mchehab+huawei@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On Mon, May 10, 2021 at 12:26:23PM +0200, Mauro Carvalho Chehab wrote: > While UTF-8 characters can be used at the Linux documentation, > the best is to use them only when ASCII doesn't offer a good replacement. > So, replace the occurences of the following UTF-8 characters: > > - U+00a0 (' '): NO-BREAK SPACE > - U+2018 ('‘'): LEFT SINGLE QUOTATION MARK > - U+2019 ('’'): RIGHT SINGLE QUOTATION MARK > > Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Mathieu Poirier > --- > .../coresight/coresight-etm4x-reference.rst | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.rst b/Documentation/trace/coresight/coresight-etm4x-reference.rst > index b64d9a9c79df..e8ddfc144d9a 100644 > --- a/Documentation/trace/coresight/coresight-etm4x-reference.rst > +++ b/Documentation/trace/coresight/coresight-etm4x-reference.rst > @@ -15,14 +15,14 @@ Root: ``/sys/bus/coresight/devices/etm`` > > The following paragraphs explain the association between sysfs files and the > ETMv4 registers that they effect. Note the register names are given without > -the ‘TRC’ prefix. > +the 'TRC' prefix. > > ---- > > :File: ``mode`` (rw) > :Trace Registers: {CONFIGR + others} > :Notes: > - Bit select trace features. See ‘mode’ section below. Bits > + Bit select trace features. See 'mode' section below. Bits > in this will cause equivalent programming of trace config and > other registers to enable the features requested. > > @@ -89,7 +89,7 @@ the ‘TRC’ prefix. > :Notes: > Pair of addresses for a range selected by addr_idx. Include > / exclude according to the optional parameter, or if omitted > - uses the current ‘mode’ setting. Select comparator range in > + uses the current 'mode' setting. Select comparator range in > control register. Error if index is odd value. > > :Depends: ``mode, addr_idx`` > @@ -277,7 +277,7 @@ the ‘TRC’ prefix. > :Trace Registers: VICTLR{23:20} > :Notes: > Program non-secure exception level filters. Set / clear NS > - exception filter bits. Setting ‘1’ excludes trace from the > + exception filter bits. Setting '1' excludes trace from the > exception level. > > :Syntax: > @@ -427,7 +427,7 @@ the ‘TRC’ prefix. > :Syntax: > ``echo idx > vmid_idx`` > > - Where idx <  numvmidc > + Where idx < numvmidc > > ---- > > @@ -628,7 +628,7 @@ the reset parameter:: > > > > -The ‘mode’ sysfs parameter. > +The 'mode' sysfs parameter. > --------------------------- > > This is a bitfield selection parameter that sets the overall trace mode for the > @@ -696,7 +696,7 @@ Bit assignments shown below:- > ETM_MODE_QELEM(val) > > **description:** > - ‘val’ determines level of Q element support enabled if > + 'val' determines level of Q element support enabled if > implemented by the ETM [IDR0] > > > @@ -780,7 +780,7 @@ Bit assignments shown below:- > ---- > > *Note a)* On startup the ETM is programmed to trace the complete address space > -using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to > +using address range comparator 0. 'mode' bits 30 / 31 modify this setting to > set EL exclude bits for NS state in either user space (EL0) or kernel space > (EL1) in the address range comparator. (the default setting excludes all > secure EL, and NS EL2) > -- > 2.30.2 >