From: Dan Carpenter <dan.carpenter@oracle.com>
To: Anup Patel <anup.patel@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Alexander Graf <graf@amazon.com>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Damien Le Moal <damien.lemoal@wdc.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev
Subject: Re: [PATCH v18 14/18] RISC-V: KVM: Implement ONE REG interface for FP registers
Date: Thu, 20 May 2021 09:09:24 +0300 [thread overview]
Message-ID: <20210520060924.GD1955@kadam> (raw)
In-Reply-To: <20210519033553.1110536-15-anup.patel@wdc.com>
On Wed, May 19, 2021 at 09:05:49AM +0530, Anup Patel wrote:
> +static int kvm_riscv_vcpu_set_reg_fp(struct kvm_vcpu *vcpu,
> + const struct kvm_one_reg *reg,
> + unsigned long rtype)
> +{
> + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
> + unsigned long isa = vcpu->arch.isa;
> + unsigned long __user *uaddr =
> + (unsigned long __user *)(unsigned long)reg->addr;
> + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
> + KVM_REG_SIZE_MASK |
> + rtype);
> + void *reg_val;
> +
> + if ((rtype == KVM_REG_RISCV_FP_F) &&
> + riscv_isa_extension_available(&isa, f)) {
> + if (KVM_REG_SIZE(reg->id) != sizeof(u32))
> + return -EINVAL;
> + if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr))
> + reg_val = &cntx->fp.f.fcsr;
> + else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <= reg_num) &&
> + reg_num <= KVM_REG_RISCV_FP_F_REG(f[31]))
> + reg_val = &cntx->fp.f.f[reg_num];
> + else
> + return -EINVAL;
> + } else if ((rtype == KVM_REG_RISCV_FP_D) &&
> + riscv_isa_extension_available(&isa, d)) {
> + if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) {
> + if (KVM_REG_SIZE(reg->id) != sizeof(u32))
> + return -EINVAL;
> + reg_val = &cntx->fp.d.fcsr;
> + } else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <= reg_num) &&
> + reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) {
> + if (KVM_REG_SIZE(reg->id) != sizeof(u64))
> + return -EINVAL;
> + reg_val = &cntx->fp.d.f[reg_num];
> + } else
> + return -EINVAL;
> + } else
> + return -EINVAL;
> +
> + if (copy_from_user(reg_val, uaddr, KVM_REG_SIZE(reg->id)))
^^^^^^^
It sort of bothers me that if this copy fails then we have no idea
what garbage is in reg_val. It would be nicer to copy it to a temporary
buffer and then memcpy it when we know it's going succeed.
> + return -EFAULT;
> +
> + return 0;
> +}
regards,
dan carpenter
next prev parent reply other threads:[~2021-05-20 6:10 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-19 3:35 [PATCH v18 00/18] KVM RISC-V Support Anup Patel
2021-05-19 3:35 ` [PATCH v18 01/18] RISC-V: Add hypervisor extension related CSR defines Anup Patel
2021-05-19 3:35 ` [PATCH v18 02/18] RISC-V: Add initial skeletal KVM support Anup Patel
2021-05-19 9:24 ` Dan Carpenter
2021-05-19 10:17 ` Dan Carpenter
2021-05-19 3:35 ` [PATCH v18 03/18] RISC-V: KVM: Implement VCPU create, init and destroy functions Anup Patel
2021-05-19 3:35 ` [PATCH v18 04/18] RISC-V: KVM: Implement VCPU interrupts and requests handling Anup Patel
2021-05-19 3:35 ` [PATCH v18 05/18] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls Anup Patel
2021-05-19 3:35 ` [PATCH v18 06/18] RISC-V: KVM: Implement VCPU world-switch Anup Patel
2021-05-19 3:35 ` [PATCH v18 07/18] RISC-V: KVM: Handle MMIO exits for VCPU Anup Patel
2021-05-19 3:35 ` [PATCH v18 08/18] RISC-V: KVM: Handle WFI " Anup Patel
2021-05-19 3:35 ` [PATCH v18 09/18] RISC-V: KVM: Implement VMID allocator Anup Patel
2021-05-19 3:35 ` [PATCH v18 10/18] RISC-V: KVM: Implement stage2 page table programming Anup Patel
2021-05-19 3:35 ` [PATCH v18 11/18] RISC-V: KVM: Implement MMU notifiers Anup Patel
2021-05-19 10:09 ` Dan Carpenter
2021-05-19 3:35 ` [PATCH v18 12/18] RISC-V: KVM: Add timer functionality Anup Patel
2021-05-19 3:35 ` [PATCH v18 13/18] RISC-V: KVM: FP lazy save/restore Anup Patel
2021-05-19 3:35 ` [PATCH v18 14/18] RISC-V: KVM: Implement ONE REG interface for FP registers Anup Patel
2021-05-19 10:11 ` Dan Carpenter
2021-05-20 6:09 ` Dan Carpenter [this message]
2021-05-19 3:35 ` [PATCH v18 15/18] RISC-V: KVM: Add SBI v0.1 support Anup Patel
2021-05-19 3:35 ` [PATCH v18 16/18] RISC-V: KVM: Document RISC-V specific parts of KVM API Anup Patel
2021-05-19 3:35 ` [PATCH v18 17/18] RISC-V: KVM: Move sources to drivers/staging directory Anup Patel
2021-05-19 3:35 ` [PATCH v18 18/18] RISC-V: KVM: Add MAINTAINERS entry Anup Patel
2021-05-19 4:58 ` [PATCH v18 00/18] KVM RISC-V Support Greg Kroah-Hartman
2021-05-19 5:10 ` Anup Patel
2021-05-19 5:21 ` Greg Kroah-Hartman
2021-05-19 10:47 ` Greg Kroah-Hartman
2021-05-19 11:18 ` Paolo Bonzini
2021-05-19 12:23 ` Greg Kroah-Hartman
2021-05-19 13:29 ` Paolo Bonzini
2021-05-19 13:58 ` Greg Kroah-Hartman
2021-05-19 15:08 ` Dan Carpenter
2021-05-19 15:26 ` Paolo Bonzini
2021-05-21 17:13 ` Palmer Dabbelt
2021-05-21 17:21 ` Paolo Bonzini
2021-05-21 17:47 ` Greg KH
2021-05-21 18:08 ` Palmer Dabbelt
2021-05-21 18:25 ` Greg KH
2021-05-21 20:25 ` Paolo Bonzini
2021-05-24 7:09 ` Guo Ren
2021-05-24 22:57 ` Palmer Dabbelt
2021-05-24 23:08 ` Damien Le Moal
2021-05-25 7:37 ` Greg KH
2021-05-25 8:01 ` Damien Le Moal
2021-05-25 8:11 ` Greg KH
2021-05-25 8:24 ` Paolo Bonzini
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