From: "David E. Box" <david.e.box@linux.intel.com>
To: lee.jones@linaro.org, hdegoede@redhat.com,
mgross@linux.intel.com, bhelgaas@google.com,
gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com,
srinivas.pandruvada@intel.com
Cc: "David E. Box" <david.e.box@linux.intel.com>,
linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
platform-driver-x86@vger.kernel.org, linux-pci@vger.kernel.org
Subject: [PATCH 1/5] PCI: Add #defines for accessing PCIe DVSEC fields
Date: Thu, 30 Sep 2021 18:28:11 -0700 [thread overview]
Message-ID: <20211001012815.1999501-2-david.e.box@linux.intel.com> (raw)
In-Reply-To: <20211001012815.1999501-1-david.e.box@linux.intel.com>
Add #defines for accessing Vendor ID, Revision, Length, and ID offsets
in the Designated Vendor Specific Extended Capability (DVSEC). Defined
in PCIe r5.0, sec 7.9.6.
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
---
V1: s/PCIE/PCIe in commit message as requested by Bjorn
include/uapi/linux/pci_regs.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index e709ae8235e7..57ee51f19283 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1080,7 +1080,11 @@
/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
#define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */
+#define PCI_DVSEC_HEADER1_VID(x) ((x) & 0xffff)
+#define PCI_DVSEC_HEADER1_REV(x) (((x) >> 16) & 0xf)
+#define PCI_DVSEC_HEADER1_LEN(x) (((x) >> 20) & 0xfff)
#define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */
+#define PCI_DVSEC_HEADER2_ID(x) ((x) & 0xffff)
/* Data Link Feature */
#define PCI_DLF_CAP 0x04 /* Capabilities Register */
--
2.25.1
next prev parent reply other threads:[~2021-10-01 1:28 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-01 1:28 [PATCH 0/5] Move intel_pm from MFD to Auxiliary bus David E. Box
2021-10-01 1:28 ` David E. Box [this message]
2021-10-01 1:28 ` [PATCH 2/5] platform/x86/intel: Move intel_pmt from MFD to Auxiliary Bus David E. Box
2021-10-06 8:58 ` Leon Romanovsky
2021-10-06 20:58 ` David E. Box
2021-10-10 6:59 ` Leon Romanovsky
2021-11-14 1:56 ` kernel test robot
2021-10-01 1:28 ` [PATCH 3/5] platform/x86/intel: extended_caps: Add support for PCIe VSEC structures David E. Box
2021-10-01 1:28 ` [PATCH 4/5] Documentation: Update ioctl-number.rst for Intel Software Defined Silicon interface David E. Box
2021-10-01 1:28 ` [PATCH 5/5] platform/x86: Add Intel Software Defined Silicon driver David E. Box
2021-10-01 7:14 ` Greg KH
2021-10-01 10:38 ` David E. Box
2021-10-01 11:29 ` Greg KH
2021-10-01 7:15 ` Greg KH
2021-10-01 7:16 ` Greg KH
2021-10-01 10:47 ` David E. Box
2021-10-01 11:27 ` Greg KH
2021-10-01 7:29 ` Greg KH
2021-10-01 11:13 ` David E. Box
2021-10-01 11:26 ` Greg KH
2021-10-01 20:43 ` David E. Box
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