From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97428C433FE for ; Wed, 18 May 2022 12:29:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236725AbiERM3S (ORCPT ); Wed, 18 May 2022 08:29:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236728AbiERM2Y (ORCPT ); Wed, 18 May 2022 08:28:24 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2523C16D49A; Wed, 18 May 2022 05:27:47 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CA9B36147D; Wed, 18 May 2022 12:27:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 454DBC36AEA; Wed, 18 May 2022 12:27:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652876866; bh=vck1sxQuINJLtEffACLVYoU+epqqYfT3LqQdONy1Zyc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V+tSXncx1kiub2uWL7HMsT/qDzr9hlCRGAVUKI62pBKKyXpfytd5LPHAbx1V1r038 bWG7t9Cb/f8qmYma7t8j96fuxNdcZ4gy/3CgYp8fGBcY4JioY2OLB6bkU/QqxbLqFz kRTEveeLTyXsadvB4FmXFHMIKsoMGa0qGDgz/BR+mfA8cwIbTnJcCSya1Kx2quP0We dr2u8xji9j+ITpveUllrLCYAKtlrXZxGFVdlK4FL6c3nIizvY3l9cYmqAMNlLEXpND T9Ds3+sm9hmdUDKhmD9b4vGLLkw7gcSYimZ3VT5AMoz1tUkB2P7XjVkGQNLkf6oBsb IJBRTJm5AWlYg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Shreyas K K , Sai Prakash Ranjan , Will Deacon , Sasha Levin , catalin.marinas@arm.com, corbet@lwn.net, suzuki.poulose@arm.com, anshuman.khandual@arm.com, mathieu.poirier@linaro.org, james.morse@arm.com, maz@kernel.org, lcherian@marvell.com, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH AUTOSEL 5.17 22/23] arm64: Enable repeat tlbi workaround on KRYO4XX gold CPUs Date: Wed, 18 May 2022 08:26:35 -0400 Message-Id: <20220518122641.342120-22-sashal@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220518122641.342120-1-sashal@kernel.org> References: <20220518122641.342120-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org From: Shreyas K K [ Upstream commit 51f559d66527e238f9a5f82027bff499784d4eac ] Add KRYO4XX gold/big cores to the list of CPUs that need the repeat TLBI workaround. Apply this to the affected KRYO4XX cores (rcpe to rfpe). The variant and revision bits are implementation defined and are different from the their Cortex CPU counterparts on which they are based on, i.e., (r0p0 to r3p0) is equivalent to (rcpe to rfpe). Signed-off-by: Shreyas K K Reviewed-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/20220512110134.12179-1-quic_shrekk@quicinc.com Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- Documentation/arm64/silicon-errata.rst | 3 +++ arch/arm64/kernel/cpu_errata.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index ea281dd75517..29b136849d30 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -189,6 +189,9 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Qualcomm Tech. | Kryo4xx Silver | N/A | ARM64_ERRATUM_1024718 | +----------------+-----------------+-----------------+-----------------------------+ +| Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_1286807 | ++----------------+-----------------+-----------------+-----------------------------+ + +----------------+-----------------+-----------------+-----------------------------+ | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 | +----------------+-----------------+-----------------+-----------------------------+ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 146fa2e76834..10c865e311a0 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -208,6 +208,8 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { #ifdef CONFIG_ARM64_ERRATUM_1286807 { ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), + /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */ + ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe), }, #endif {}, -- 2.35.1