linux-doc.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>, Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Jonathan Corbet <corbet@lwn.net>,
	Anup Patel <apatel@ventanamicro.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Atish Patra <atishp@rivosinc.com>,
	'Conor Dooley ' <conor.dooley@microchip.com>,
	Sunil V L <sunilvl@ventanamicro.com>,
	"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>
Subject: [PATCH V3 15/20] clocksource/timer-riscv: Refactor riscv_timer_init_dt()
Date: Fri,  3 Mar 2023 19:06:42 +0530	[thread overview]
Message-ID: <20230303133647.845095-16-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com>

Refactor the timer init function such that few things can be
shared by both DT and ACPI based platforms.

Co-developed-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 drivers/clocksource/timer-riscv.c | 81 +++++++++++++++----------------
 1 file changed, 40 insertions(+), 41 deletions(-)

diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 5f0f10c7e222..cecc4662293b 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -124,61 +124,28 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-static int __init riscv_timer_init_dt(struct device_node *n)
+static int __init riscv_timer_init_common(void)
 {
-	int cpuid, error;
-	unsigned long hartid;
-	struct device_node *child;
+	int error;
 	struct irq_domain *domain;
+	struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode();
 
-	error = riscv_of_processor_hartid(n, &hartid);
-	if (error < 0) {
-		pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n",
-			n, hartid);
-		return error;
-	}
-
-	cpuid = riscv_hartid_to_cpuid(hartid);
-	if (cpuid < 0) {
-		pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
-		return cpuid;
-	}
-
-	if (cpuid != smp_processor_id())
-		return 0;
-
-	child = of_find_compatible_node(NULL, NULL, "riscv,timer");
-	if (child) {
-		riscv_timer_cannot_wake_cpu = of_property_read_bool(child,
-					"riscv,timer-cannot-wake-cpu");
-		of_node_put(child);
-	}
-
-	domain = NULL;
-	child = of_get_compatible_child(n, "riscv,cpu-intc");
-	if (!child) {
-		pr_err("Failed to find INTC node [%pOF]\n", n);
-		return -ENODEV;
-	}
-	domain = irq_find_host(child);
-	of_node_put(child);
+	domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY);
 	if (!domain) {
-		pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
+		pr_err("Failed to find irq_domain for INTC node [%pfwP]\n",
+		       intc_fwnode);
 		return -ENODEV;
 	}
 
 	riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
 	if (!riscv_clock_event_irq) {
-		pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
+		pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode);
 		return -ENODEV;
 	}
 
-	pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n",
-	       __func__, cpuid, hartid);
 	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
 	if (error) {
-		pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
-		       error, cpuid);
+		pr_err("RISCV timer registration failed [%d]\n", error);
 		return error;
 	}
 
@@ -207,4 +174,36 @@ static int __init riscv_timer_init_dt(struct device_node *n)
 	return error;
 }
 
+static int __init riscv_timer_init_dt(struct device_node *n)
+{
+	int cpuid, error;
+	unsigned long hartid;
+	struct device_node *child;
+
+	error = riscv_of_processor_hartid(n, &hartid);
+	if (error < 0) {
+		pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n",
+			n, hartid);
+		return error;
+	}
+
+	cpuid = riscv_hartid_to_cpuid(hartid);
+	if (cpuid < 0) {
+		pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
+		return cpuid;
+	}
+
+	if (cpuid != smp_processor_id())
+		return 0;
+
+	child = of_find_compatible_node(NULL, NULL, "riscv,timer");
+	if (child) {
+		riscv_timer_cannot_wake_cpu = of_property_read_bool(child,
+					"riscv,timer-cannot-wake-cpu");
+		of_node_put(child);
+	}
+
+	return riscv_timer_init_common();
+}
+
 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
-- 
2.34.1


  parent reply	other threads:[~2023-03-03 13:39 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-03 13:36 [PATCH V3 00/20] Add basic ACPI support for RISC-V Sunil V L
2023-03-03 13:36 ` [PATCH V3 01/20] riscv: move sbi_init() earlier before jump_label_init() Sunil V L
2023-03-03 13:36 ` [PATCH V3 02/20] ACPICA: MADT: Add RISC-V INTC interrupt controller Sunil V L
2023-03-03 13:36 ` [PATCH V3 03/20] ACPICA: Add structure definitions for RISC-V RHCT Sunil V L
2023-03-03 13:36 ` [PATCH V3 04/20] ACPI: tables: Print RINTC information when MADT is parsed Sunil V L
2023-03-03 14:58   ` Andrew Jones
2023-03-03 13:36 ` [PATCH V3 05/20] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Sunil V L
2023-03-03 13:36 ` [PATCH V3 06/20] RISC-V: Add support to build the ACPI core Sunil V L
2023-03-03 15:36   ` Andrew Jones
2023-03-04 14:38     ` Andrew Jones
2023-03-06 20:00   ` Conor Dooley
2023-03-03 13:36 ` [PATCH V3 07/20] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Sunil V L
2023-03-03 13:36 ` [PATCH V3 08/20] drivers/acpi: RISC-V: Add RHCT related code Sunil V L
2023-03-03 13:36 ` [PATCH V3 09/20] RISC-V: smpboot: Create wrapper smp_setup() Sunil V L
2023-03-03 13:36 ` [PATCH V3 10/20] RISC-V: smpboot: Add ACPI support in smp_setup() Sunil V L
2023-03-03 15:49   ` Andrew Jones
2023-03-03 17:54     ` Sunil V L
2023-03-03 13:36 ` [PATCH V3 11/20] RISC-V: ACPI: Cache and retrieve the RINTC structure Sunil V L
2023-03-03 16:05   ` Andrew Jones
2023-03-03 16:58     ` Conor Dooley
2023-03-03 17:21       ` Andrew Jones
2023-03-03 17:49         ` Sunil V L
2023-03-03 17:58     ` Sunil V L
2023-03-03 18:04       ` Andrew Jones
2023-03-03 18:17         ` Sunil V L
2023-03-03 13:36 ` [PATCH V3 12/20] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Sunil V L
2023-03-03 16:16   ` Andrew Jones
2023-03-03 17:55     ` Sunil V L
2023-03-06 20:26   ` Conor Dooley
2023-03-03 13:36 ` [PATCH V3 13/20] RISC-V: cpu: Enable cpuinfo for ACPI systems Sunil V L
2023-03-03 16:18   ` Andrew Jones
2023-03-06 20:39   ` Conor Dooley
2023-03-03 13:36 ` [PATCH V3 14/20] irqchip/riscv-intc: Add ACPI support Sunil V L
2023-03-06 20:53   ` Conor Dooley
2023-03-03 13:36 ` Sunil V L [this message]
2023-03-06 21:01   ` [PATCH V3 15/20] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Conor Dooley
2023-03-03 13:36 ` [PATCH V3 16/20] clocksource/timer-riscv: Add ACPI support Sunil V L
2023-03-06 21:06   ` Conor Dooley
2023-03-03 13:36 ` [PATCH V3 17/20] RISC-V: time.c: Add ACPI support for time_init() Sunil V L
2023-03-06 21:09   ` Conor Dooley
2023-03-08  9:43     ` Sunil V L
2023-03-03 13:36 ` [PATCH V3 18/20] RISC-V: Add ACPI initialization in setup_arch() Sunil V L
2023-03-06 21:17   ` Conor Dooley
2023-03-08  9:42     ` Sunil V L
2023-03-08 10:21       ` Conor Dooley
2023-03-03 13:36 ` [PATCH V3 19/20] RISC-V: Enable ACPI in defconfig Sunil V L
2023-03-03 16:23   ` Andrew Jones
2023-03-06 21:18   ` Conor Dooley
2023-03-03 13:36 ` [PATCH V3 20/20] MAINTAINERS: Add entry for drivers/acpi/riscv Sunil V L
2023-03-06 21:51 ` [PATCH V3 00/20] Add basic ACPI support for RISC-V Conor Dooley
2023-03-07  5:06   ` Sunil V L
2023-03-07  6:13     ` Conor Dooley
2023-03-07 18:44       ` Conor Dooley
2023-03-08  1:01         ` Sunil V L
2023-04-04  6:35           ` Ley Foon Tan
2023-04-04  6:54             ` Sunil V L
2023-04-06  2:45               ` Atish Kumar Patra
2023-04-19  8:07                 ` Ley Foon Tan
2023-04-19 23:34                   ` Atish Patra

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230303133647.845095-16-sunilvl@ventanamicro.com \
    --to=sunilvl@ventanamicro.com \
    --cc=ajones@ventanamicro.com \
    --cc=aou@eecs.berkeley.edu \
    --cc=apatel@ventanamicro.com \
    --cc=atishp@rivosinc.com \
    --cc=conor.dooley@microchip.com \
    --cc=corbet@lwn.net \
    --cc=daniel.lezcano@linaro.org \
    --cc=lenb@kernel.org \
    --cc=linux-acpi@vger.kernel.org \
    --cc=linux-doc@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=maz@kernel.org \
    --cc=palmer@dabbelt.com \
    --cc=rafael.j.wysocki@intel.com \
    --cc=rafael@kernel.org \
    --cc=tglx@linutronix.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).