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From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>, Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Jonathan Corbet <corbet@lwn.net>,
	Anup Patel <apatel@ventanamicro.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Atish Patra <atishp@rivosinc.com>,
	'Conor Dooley ' <conor.dooley@microchip.com>,
	Sunil V L <sunilvl@ventanamicro.com>,
	"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>
Subject: [PATCH V3 06/20] RISC-V: Add support to build the ACPI core
Date: Fri,  3 Mar 2023 19:06:33 +0530	[thread overview]
Message-ID: <20230303133647.845095-7-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com>

Enable ACPI core for RISC-V after adding architecture-specific
interfaces and header files required to build the ACPI core.

1) Couple of header files are required unconditionally by the ACPI
core. Add empty acenv.h and cpu.h header files.

2) If CONFIG_PCI is enabled, a few PCI related interfaces need to
be provided by the architecture. Define dummy interfaces for now
so that build succeeds. Actual implementation will be added when
PCI support is added for ACPI along with external interrupt
controller support.

3) A few globals and memory mapping related functions specific
to the architecture need to be provided.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 arch/riscv/Kconfig             |  5 +++
 arch/riscv/include/asm/acenv.h | 11 +++++
 arch/riscv/include/asm/acpi.h  | 61 ++++++++++++++++++++++++++
 arch/riscv/include/asm/cpu.h   |  8 ++++
 arch/riscv/kernel/Makefile     |  2 +
 arch/riscv/kernel/acpi.c       | 80 ++++++++++++++++++++++++++++++++++
 6 files changed, 167 insertions(+)
 create mode 100644 arch/riscv/include/asm/acenv.h
 create mode 100644 arch/riscv/include/asm/acpi.h
 create mode 100644 arch/riscv/include/asm/cpu.h
 create mode 100644 arch/riscv/kernel/acpi.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 71754eb32ee6..f3108c7e19d8 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -12,6 +12,8 @@ config 32BIT
 
 config RISCV
 	def_bool y
+	select ACPI_GENERIC_GSI if ACPI
+	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
 	select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
 	select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
 	select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
@@ -617,6 +619,7 @@ config EFI
 	depends on OF && !XIP_KERNEL
 	depends on MMU
 	default y
+	select ARCH_SUPPORTS_ACPI if 64BIT
 	select EFI_GENERIC_STUB
 	select EFI_PARAMS_FROM_FDT
 	select EFI_RUNTIME_WRAPPERS
@@ -720,3 +723,5 @@ source "drivers/cpufreq/Kconfig"
 endmenu # "CPU Power Management"
 
 source "arch/riscv/kvm/Kconfig"
+
+source "drivers/acpi/Kconfig"
diff --git a/arch/riscv/include/asm/acenv.h b/arch/riscv/include/asm/acenv.h
new file mode 100644
index 000000000000..22123c5a4883
--- /dev/null
+++ b/arch/riscv/include/asm/acenv.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * RISC-V specific ACPICA environments and implementation
+ */
+
+#ifndef _ASM_ACENV_H
+#define _ASM_ACENV_H
+
+/* It is required unconditionally by ACPI core */
+
+#endif /* _ASM_ACENV_H */
diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h
new file mode 100644
index 000000000000..0b52a190f71a
--- /dev/null
+++ b/arch/riscv/include/asm/acpi.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *  Copyright (C) 2013-2014, Linaro Ltd.
+ *	Author: Al Stone <al.stone@linaro.org>
+ *	Author: Graeme Gregory <graeme.gregory@linaro.org>
+ *	Author: Hanjun Guo <hanjun.guo@linaro.org>
+ *
+ *  Copyright (C) 2021-2023, Ventana Micro Systems Inc.
+ *	Author: Sunil V L <sunilvl@ventanamicro.com>
+ */
+
+#ifndef _ASM_ACPI_H
+#define _ASM_ACPI_H
+
+/* Basic configuration for ACPI */
+#ifdef CONFIG_ACPI
+
+/* ACPI table mapping after acpi_permanent_mmap is set */
+void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size);
+#define acpi_os_ioremap acpi_os_ioremap
+
+#define acpi_strict 1   /* No out-of-spec workarounds on RISC-V */
+extern int acpi_disabled;
+extern int acpi_noirq;
+extern int acpi_pci_disabled;
+
+static inline void disable_acpi(void)
+{
+	acpi_disabled = 1;
+	acpi_pci_disabled = 1;
+	acpi_noirq = 1;
+}
+
+static inline void enable_acpi(void)
+{
+	acpi_disabled = 0;
+	acpi_pci_disabled = 0;
+	acpi_noirq = 0;
+}
+
+/*
+ * The ACPI processor driver for ACPI core code needs this macro
+ * to find out this cpu was already mapped (mapping from CPU hardware
+ * ID to CPU logical ID) or not.
+ */
+#define cpu_physical_id(cpu) cpuid_to_hartid_map(cpu)
+
+/*
+ * Since MADT must provide at least one RINTC structure, the
+ * CPU will be always available in MADT on RISC-V.
+ */
+static inline bool acpi_has_cpu_in_madt(void)
+{
+	return true;
+}
+
+static inline void arch_fix_phys_package_id(int num, u32 slot) { }
+
+#endif /* CONFIG_ACPI */
+
+#endif /*_ASM_ACPI_H*/
diff --git a/arch/riscv/include/asm/cpu.h b/arch/riscv/include/asm/cpu.h
new file mode 100644
index 000000000000..ea1a88b3d5f2
--- /dev/null
+++ b/arch/riscv/include/asm/cpu.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _ASM_CPU_H
+#define _ASM_CPU_H
+
+/* It is required unconditionally by ACPI core */
+
+#endif /* _ASM_CPU_H */
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index 67f542be1bea..f979dc8cf47d 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -90,3 +90,5 @@ obj-$(CONFIG_EFI)		+= efi.o
 obj-$(CONFIG_COMPAT)		+= compat_syscall_table.o
 obj-$(CONFIG_COMPAT)		+= compat_signal.o
 obj-$(CONFIG_COMPAT)		+= compat_vdso/
+
+obj-$(CONFIG_ACPI)              += acpi.o
diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c
new file mode 100644
index 000000000000..81d448c41714
--- /dev/null
+++ b/arch/riscv/kernel/acpi.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ *  RISC-V Specific Low-Level ACPI Boot Support
+ *
+ *  Copyright (C) 2013-2014, Linaro Ltd.
+ *	Author: Al Stone <al.stone@linaro.org>
+ *	Author: Graeme Gregory <graeme.gregory@linaro.org>
+ *	Author: Hanjun Guo <hanjun.guo@linaro.org>
+ *	Author: Tomasz Nowicki <tomasz.nowicki@linaro.org>
+ *	Author: Naresh Bhat <naresh.bhat@linaro.org>
+ *
+ *  Copyright (C) 2021-2023, Ventana Micro Systems Inc.
+ *	Author: Sunil V L <sunilvl@ventanamicro.com>
+ */
+
+#include <linux/acpi.h>
+#include <linux/io.h>
+#include <linux/pci.h>
+
+int acpi_noirq = 1;		/* skip ACPI IRQ initialization */
+int acpi_disabled = 1;
+EXPORT_SYMBOL(acpi_disabled);
+
+int acpi_pci_disabled = 1;	/* skip ACPI PCI scan and IRQ initialization */
+EXPORT_SYMBOL(acpi_pci_disabled);
+
+/*
+ * __acpi_map_table() will be called before paging_init(), so early_ioremap()
+ * or early_memremap() should be called here to for ACPI table mapping.
+ */
+void __init __iomem *__acpi_map_table(unsigned long phys, unsigned long size)
+{
+	if (!size)
+		return NULL;
+
+	return early_memremap(phys, size);
+}
+
+void __init __acpi_unmap_table(void __iomem *map, unsigned long size)
+{
+	if (!map || !size)
+		return;
+
+	early_memunmap(map, size);
+}
+
+void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size)
+{
+	return memremap(phys, size, MEMREMAP_WB);
+}
+
+#ifdef CONFIG_PCI
+
+/*
+ * These interfaces are defined just to enable building ACPI core.
+ * TODO: Update it with actual implementation when external interrupt
+ * controller support is added in RISC-V ACPI.
+ */
+int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
+		 int reg, int len, u32 *val)
+{
+	return PCIBIOS_DEVICE_NOT_FOUND;
+}
+
+int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
+		  int reg, int len, u32 val)
+{
+	return PCIBIOS_DEVICE_NOT_FOUND;
+}
+
+int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
+{
+	return -1;
+}
+
+struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
+{
+	return NULL;
+}
+#endif	/* CONFIG_PCI */
-- 
2.34.1


  parent reply	other threads:[~2023-03-03 13:38 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-03 13:36 [PATCH V3 00/20] Add basic ACPI support for RISC-V Sunil V L
2023-03-03 13:36 ` [PATCH V3 01/20] riscv: move sbi_init() earlier before jump_label_init() Sunil V L
2023-03-03 13:36 ` [PATCH V3 02/20] ACPICA: MADT: Add RISC-V INTC interrupt controller Sunil V L
2023-03-03 13:36 ` [PATCH V3 03/20] ACPICA: Add structure definitions for RISC-V RHCT Sunil V L
2023-03-03 13:36 ` [PATCH V3 04/20] ACPI: tables: Print RINTC information when MADT is parsed Sunil V L
2023-03-03 14:58   ` Andrew Jones
2023-03-03 13:36 ` [PATCH V3 05/20] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Sunil V L
2023-03-03 13:36 ` Sunil V L [this message]
2023-03-03 15:36   ` [PATCH V3 06/20] RISC-V: Add support to build the ACPI core Andrew Jones
2023-03-04 14:38     ` Andrew Jones
2023-03-06 20:00   ` Conor Dooley
2023-03-03 13:36 ` [PATCH V3 07/20] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Sunil V L
2023-03-03 13:36 ` [PATCH V3 08/20] drivers/acpi: RISC-V: Add RHCT related code Sunil V L
2023-03-03 13:36 ` [PATCH V3 09/20] RISC-V: smpboot: Create wrapper smp_setup() Sunil V L
2023-03-03 13:36 ` [PATCH V3 10/20] RISC-V: smpboot: Add ACPI support in smp_setup() Sunil V L
2023-03-03 15:49   ` Andrew Jones
2023-03-03 17:54     ` Sunil V L
2023-03-03 13:36 ` [PATCH V3 11/20] RISC-V: ACPI: Cache and retrieve the RINTC structure Sunil V L
2023-03-03 16:05   ` Andrew Jones
2023-03-03 16:58     ` Conor Dooley
2023-03-03 17:21       ` Andrew Jones
2023-03-03 17:49         ` Sunil V L
2023-03-03 17:58     ` Sunil V L
2023-03-03 18:04       ` Andrew Jones
2023-03-03 18:17         ` Sunil V L
2023-03-03 13:36 ` [PATCH V3 12/20] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Sunil V L
2023-03-03 16:16   ` Andrew Jones
2023-03-03 17:55     ` Sunil V L
2023-03-06 20:26   ` Conor Dooley
2023-03-03 13:36 ` [PATCH V3 13/20] RISC-V: cpu: Enable cpuinfo for ACPI systems Sunil V L
2023-03-03 16:18   ` Andrew Jones
2023-03-06 20:39   ` Conor Dooley
2023-03-03 13:36 ` [PATCH V3 14/20] irqchip/riscv-intc: Add ACPI support Sunil V L
2023-03-06 20:53   ` Conor Dooley
2023-03-03 13:36 ` [PATCH V3 15/20] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Sunil V L
2023-03-06 21:01   ` Conor Dooley
2023-03-03 13:36 ` [PATCH V3 16/20] clocksource/timer-riscv: Add ACPI support Sunil V L
2023-03-06 21:06   ` Conor Dooley
2023-03-03 13:36 ` [PATCH V3 17/20] RISC-V: time.c: Add ACPI support for time_init() Sunil V L
2023-03-06 21:09   ` Conor Dooley
2023-03-08  9:43     ` Sunil V L
2023-03-03 13:36 ` [PATCH V3 18/20] RISC-V: Add ACPI initialization in setup_arch() Sunil V L
2023-03-06 21:17   ` Conor Dooley
2023-03-08  9:42     ` Sunil V L
2023-03-08 10:21       ` Conor Dooley
2023-03-03 13:36 ` [PATCH V3 19/20] RISC-V: Enable ACPI in defconfig Sunil V L
2023-03-03 16:23   ` Andrew Jones
2023-03-06 21:18   ` Conor Dooley
2023-03-03 13:36 ` [PATCH V3 20/20] MAINTAINERS: Add entry for drivers/acpi/riscv Sunil V L
2023-03-06 21:51 ` [PATCH V3 00/20] Add basic ACPI support for RISC-V Conor Dooley
2023-03-07  5:06   ` Sunil V L
2023-03-07  6:13     ` Conor Dooley
2023-03-07 18:44       ` Conor Dooley
2023-03-08  1:01         ` Sunil V L
2023-04-04  6:35           ` Ley Foon Tan
2023-04-04  6:54             ` Sunil V L
2023-04-06  2:45               ` Atish Kumar Patra
2023-04-19  8:07                 ` Ley Foon Tan
2023-04-19 23:34                   ` Atish Patra

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