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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id t26-20020a1709060c5a00b008ec793ac3f4sm1146250ejf.192.2023.03.03.09.21.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 09:21:14 -0800 (PST) Date: Fri, 3 Mar 2023 18:21:13 +0100 From: Andrew Jones To: Conor Dooley Cc: Sunil V L , linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Atish Patra , 'Conor Dooley ' , "Rafael J . Wysocki" Subject: Re: [PATCH V3 11/20] RISC-V: ACPI: Cache and retrieve the RINTC structure Message-ID: <20230303172113.jskripuyr3xx2z7k@orel> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> <20230303133647.845095-12-sunilvl@ventanamicro.com> <20230303160556.lezccmwa7ymymxws@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On Fri, Mar 03, 2023 at 04:58:53PM +0000, Conor Dooley wrote: > On Fri, Mar 03, 2023 at 05:05:56PM +0100, Andrew Jones wrote: > > On Fri, Mar 03, 2023 at 07:06:38PM +0530, Sunil V L wrote: > > > RINTC structures in the MADT provide mapping between the hartid > > > and the CPU. This is required many times even at run time like > > > cpuinfo. So, instead of parsing the ACPI table every time, cache > > > the RINTC structures and provide a function to get the correct > > > RINTC structure for a given cpu. > > > > > > Signed-off-by: Sunil V L > > > Acked-by: Rafael J. Wysocki > > > --- > > > arch/riscv/include/asm/acpi.h | 9 ++++++ > > > arch/riscv/kernel/acpi.c | 56 +++++++++++++++++++++++++++++++++++ > > > 2 files changed, 65 insertions(+) > > > > diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h > > > index 111a8ed10af1..8be16c1ef7da 100644 > > > --- a/arch/riscv/include/asm/acpi.h > > > +++ b/arch/riscv/include/asm/acpi.h > > > @@ -61,6 +61,10 @@ static inline void arch_fix_phys_package_id(int num, u32 slot) { } > > > > > > int acpi_get_riscv_isa(struct acpi_table_header *table, > > > unsigned int cpu, const char **isa); > > > + > > > +struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu); > > > + > > > +u32 get_acpi_id_for_cpu(int cpu); > > > #else > > > static inline int acpi_get_riscv_isa(struct acpi_table_header *table, > > > unsigned int cpu, const char **isa) > > > @@ -68,6 +72,11 @@ static inline int acpi_get_riscv_isa(struct acpi_table_header *table, > > > return -EINVAL; > > > } > > > > > > +static inline u32 get_acpi_id_for_cpu(int cpu) > > > +{ > > > + return -1; > > > +} > > > > Why do we need this stub? I wouldn't expect non-ACPI code to need an ACPI > > ID. > > I think I asked for this (or assumed it existed) in v1, when I requested > the removal of #ifdef CONFIG_ACPI stuff in riscv_fill_hwcap(). > Personally, I'd rather have this stub than the ifdeffery :) > Yeah, avoiding #ifdefs with stubs is good if we need to call the function from non-ACPI code. I'm wondering why we'd need to, though. In all the cases introduced with this series, we could pass a 'cpu' to acpi_get_riscv_isa() and then have acpi_get_riscv_isa() call get_acpi_id_for_cpu() itself, for example. We also need to be sure -1 truly means "no ACPI ID" in order to stub this. Thanks, drew