From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90D20C76195 for ; Mon, 27 Mar 2023 16:32:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232437AbjC0Qcb (ORCPT ); Mon, 27 Mar 2023 12:32:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232411AbjC0Qc2 (ORCPT ); Mon, 27 Mar 2023 12:32:28 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D2C462713 for ; Mon, 27 Mar 2023 09:32:25 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id f6-20020a17090ac28600b0023b9bf9eb63so9464926pjt.5 for ; Mon, 27 Mar 2023 09:32:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1679934745; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DS7/SOsXai4Z1GKznU9FqGZtfi0arBEE5QT+dGbkbBE=; b=3lMM3H8U18ZqUbaeF2VJRt0lHe7jyqdRt37VFG5QO2VrYaw8TBsbbgAiIX12YxDlxl REAoc3qfyltvjObTtNm8Zzd5zMmT65U9utSxdOO6yJWzGvjnD2IKq9WtNkDq4I3TkSEb lg2XTMMR6QYYh85ZN2xD9Q1WyTQ1nNvDwNiE00WrFI25lDU8xOw0l6MKR9PW8OqemJKa JuOAqmnvJIa6aMNFJnZ29YIfezY3Tx3BW1NAsy/kyYdwqAHqNPvrt+YSW6WdplM2YxJS NYmZUwF9OFQ4cX41uS9kM/3qo8UfPoWDNw+XLURqvvvLZGZU/O/k7E70urDAOCXa74am ajGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679934745; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DS7/SOsXai4Z1GKznU9FqGZtfi0arBEE5QT+dGbkbBE=; b=VuYBpUpvWiUzh42/6M5/xZ+W1ZP4aY2rOqEMLAUejl09Rds8WH4IpjZsLZ0E24AtD7 YrzDOv82LUDVSg6ofCsYEkEAFUd+DXhVJ1ocrE7rNdtL/M+w1H5/fzz+bwakqaZ0VsSy O1/TGq/DlZ8++zAyrGZaTdeU1Iy1COaja7DtDVFDGht5pt9UN8GKcX6Mw4n3RNKec6zK rXiNilMEeNmHhS+TlNoE8ju24dBKugYZ0m9BZet2/E3YYU6Z06PRPrwFZNU/wPGCK/as YRFKuM03k4ZL9vCxbKCa74nmWJptmJMKwYhqHwmc1L3j0P42HDfP8fsTP2P59fBk/LzY B2Tg== X-Gm-Message-State: AAQBX9c2gim+SBeurCyWJe65vwAm9TXml4OR4zOaBjMOdhyTOEOs6x9V sUNa6RmydJ7WQqFgbOLokKucdg== X-Google-Smtp-Source: AKy350Z6lmWh84+PK+zp0auYZJ6hFzt64IzvMQMXjMMnQ1plLYt7qTpC7cqYDdnYX4Y4tnRTo4K85A== X-Received: by 2002:a17:903:94:b0:1a1:b506:6fe with SMTP id o20-20020a170903009400b001a1b50606femr9617322pld.29.1679934745233; Mon, 27 Mar 2023 09:32:25 -0700 (PDT) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id io20-20020a17090312d400b001a1faeac240sm8963524plb.186.2023.03.27.09.32.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 09:32:24 -0700 (PDT) From: Evan Green To: Palmer Dabbelt Cc: slewis@rivosinc.com, vineetg@rivosinc.com, heiko@sntech.de, Conor Dooley , Evan Green , Conor Dooley , Heiko Stuebner , Albert Ou , Andrew Bresticker , Celeste Liu , Guo Ren , Jonathan Corbet , Palmer Dabbelt , Paul Walmsley , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v5 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Date: Mon, 27 Mar 2023 09:32:00 -0700 Message-Id: <20230327163203.2918455-4-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230327163203.2918455-1-evan@rivosinc.com> References: <20230327163203.2918455-1-evan@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org We have an implicit set of base behaviors that userspace depends on, which are mostly defined in various ISA specifications. Co-developed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- Changes in v5: - Fixed misuse of ISA_EXT_c as bitmap, changed to use riscv_isa_extension_available() (Heiko, Conor) Changes in v4: - More newlines in BASE_BEHAVIOR_IMA documentation (Conor) Changes in v3: - Refactored base ISA behavior probe to allow kernel probing as well, in prep for vDSO data initialization. - Fixed doc warnings in IMA text list, use :c:macro:. Documentation/riscv/hwprobe.rst | 24 ++++++++++++++++++++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 5 +++++ arch/riscv/kernel/sys_riscv.c | 20 ++++++++++++++++++++ 4 files changed, 50 insertions(+), 1 deletion(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 211828f706e3..945d44683c40 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -39,3 +39,27 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_KEY_MIMPLID`: Contains the value of ``mimplid``, as defined by the RISC-V privileged architecture specification. + +* :c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`: A bitmask containing the base + user-visible behavior that this kernel supports. The following base user ABIs + are defined: + + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or + rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the + privileged ISA, with the following known exceptions (more exceptions may be + added, but only if it can be demonstrated that the user ABI is not broken): + + * The :fence.i: instruction cannot be directly executed by userspace + programs (it may still be executed in userspace via a + kernel-controlled mechanism such as the vDSO). + +* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions + that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: + base system behavior. + + * :c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as + defined by commit cd20cee ("FMIN/FMAX now implement + minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual. + + * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined + by version 2.2 of the RISC-V ISA manual. diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 08d1c3bdd78a..7e52f1e1fe10 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,6 +8,6 @@ #include -#define RISCV_HWPROBE_MAX_KEY 2 +#define RISCV_HWPROBE_MAX_KEY 4 #endif diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 591802047460..fc5665411782 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -20,6 +20,11 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_MVENDORID 0 #define RISCV_HWPROBE_KEY_MARCHID 1 #define RISCV_HWPROBE_KEY_MIMPID 2 +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4 +#define RISCV_HWPROBE_IMA_FD (1 << 0) +#define RISCV_HWPROBE_IMA_C (1 << 1) /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ #endif diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 981d23457f13..c83218a0db02 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -125,6 +126,25 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, case RISCV_HWPROBE_KEY_MIMPID: hwprobe_arch_id(pair, cpus); break; + /* + * The kernel already assumes that the base single-letter ISA + * extensions are supported on all harts, and only supports the + * IMA base, so just cheat a bit here and tell that to + * userspace. + */ + case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: + pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; + break; + + case RISCV_HWPROBE_KEY_IMA_EXT_0: + pair->value = 0; + if (has_fpu()) + pair->value |= RISCV_HWPROBE_IMA_FD; + + if (riscv_isa_extension_available(NULL, c)) + pair->value |= RISCV_HWPROBE_IMA_C; + + break; /* * For forward compatibility, unknown keys don't fail the whole -- 2.25.1