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From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
	linux-crypto@vger.kernel.org,
	platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev
Cc: Jonathan Corbet <corbet@lwn.net>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Weili Qian <qianweili@huawei.com>,
	Zhou Wang <wangzhou1@hisilicon.com>,
	Herbert Xu <herbert@gondor.apana.org.au>,
	"David S . Miller" <davem@davemloft.net>,
	Marc Zyngier <maz@kernel.org>,
	Maximilian Luz <luzmaximilian@gmail.com>,
	Hans de Goede <hdegoede@redhat.com>,
	Mark Gross <markgross@kernel.org>,
	Nathan Chancellor <nathan@kernel.org>,
	Nick Desaulniers <ndesaulniers@google.com>,
	Tom Rix <trix@redhat.com>, Sunil V L <sunilvl@ventanamicro.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH V5 12/21] RISC-V: only iterate over possible CPUs in ISA string parser
Date: Mon,  8 May 2023 17:22:28 +0530	[thread overview]
Message-ID: <20230508115237.216337-13-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com>

During boot we call riscv_of_processor_hartid() for each hart that we
add to the possible cpus list. Repeating the call again here is not
required, if we iterate over the list of possible CPUs, rather than the
list of all CPUs.

The call to of_property_read_string() for "riscv,isa" cannot fail
either, as it has previously succeeded in riscv_of_processor_hartid(),
but leaving in the error checking makes the operation of the loop more
obvious & provides leeway for future refactoring of
riscv_of_processor_hartid().

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 arch/riscv/kernel/cpufeature.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index b1d6b7e4b829..c607db2c842c 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -12,6 +12,7 @@
 #include <linux/memory.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <asm/alternative.h>
 #include <asm/cacheflush.h>
 #include <asm/cpufeature.h>
@@ -99,7 +100,7 @@ void __init riscv_fill_hwcap(void)
 	char print_str[NUM_ALPHA_EXTS + 1];
 	int i, j, rc;
 	unsigned long isa2hwcap[26] = {0};
-	unsigned long hartid;
+	unsigned int cpu;
 
 	isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
 	isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
@@ -112,16 +113,20 @@ void __init riscv_fill_hwcap(void)
 
 	bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
 
-	for_each_of_cpu_node(node) {
+	for_each_possible_cpu(cpu) {
 		unsigned long this_hwcap = 0;
 		DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
 		const char *temp;
 
-		rc = riscv_of_processor_hartid(node, &hartid);
-		if (rc < 0)
+		node = of_cpu_device_node_get(cpu);
+		if (!node) {
+			pr_warn("Unable to find cpu node\n");
 			continue;
+		}
 
-		if (of_property_read_string(node, "riscv,isa", &isa)) {
+		rc = of_property_read_string(node, "riscv,isa", &isa);
+		of_node_put(node);
+		if (rc) {
 			pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
 			continue;
 		}
-- 
2.34.1


  parent reply	other threads:[~2023-05-08 11:56 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-08 11:52 [PATCH V5 00/21] Add basic ACPI support for RISC-V Sunil V L
2023-05-08 11:52 ` [PATCH V5 01/21] riscv: move sbi_init() earlier before jump_label_init() Sunil V L
2023-05-08 11:52 ` [PATCH V5 02/21] platform/surface: Disable for RISC-V Sunil V L
2023-05-08 11:52 ` [PATCH V5 03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang Sunil V L
2023-05-09  2:17   ` Herbert Xu
2023-05-10  5:47     ` Sunil V L
2023-05-08 11:52 ` [PATCH V5 04/21] ACPI: tables: Print RINTC information when MADT is parsed Sunil V L
2023-05-08 11:52 ` [PATCH V5 05/21] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Sunil V L
2023-05-08 11:52 ` [PATCH V5 06/21] RISC-V: Add support to build the ACPI core Sunil V L
2023-05-08 11:52 ` [PATCH V5 07/21] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Sunil V L
2023-05-08 11:52 ` [PATCH V5 08/21] RISC-V: ACPI: Cache and retrieve the RINTC structure Sunil V L
2023-05-09 17:50   ` Conor Dooley
2023-05-10  3:46     ` Sunil V L
2023-05-08 11:52 ` [PATCH V5 09/21] drivers/acpi: RISC-V: Add RHCT related code Sunil V L
2023-05-08 11:52 ` [PATCH V5 10/21] RISC-V: smpboot: Create wrapper setup_smp() Sunil V L
2023-05-08 11:52 ` [PATCH V5 11/21] RISC-V: smpboot: Add ACPI support in setup_smp() Sunil V L
2023-05-08 11:52 ` Sunil V L [this message]
2023-05-08 11:52 ` [PATCH V5 13/21] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Sunil V L
2023-05-08 11:52 ` [PATCH V5 14/21] RISC-V: cpu: Enable cpuinfo for ACPI systems Sunil V L
2023-05-08 11:52 ` [PATCH V5 15/21] irqchip/riscv-intc: Add ACPI support Sunil V L
2023-05-08 11:52 ` [PATCH V5 16/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Sunil V L
2023-05-08 11:52 ` [PATCH V5 17/21] clocksource/timer-riscv: Add ACPI support Sunil V L
2023-05-08 11:52 ` [PATCH V5 18/21] RISC-V: time.c: Add ACPI support for time_init() Sunil V L
2023-05-08 11:52 ` [PATCH V5 19/21] RISC-V: Add ACPI initialization in setup_arch() Sunil V L
2023-05-08 11:52 ` [PATCH V5 20/21] RISC-V: Enable ACPI in defconfig Sunil V L
2023-05-08 11:52 ` [PATCH V5 21/21] MAINTAINERS: Add entry for drivers/acpi/riscv Sunil V L

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