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From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
	linux-crypto@vger.kernel.org,
	platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev
Cc: Jonathan Corbet <corbet@lwn.net>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Weili Qian <qianweili@huawei.com>,
	Zhou Wang <wangzhou1@hisilicon.com>,
	Herbert Xu <herbert@gondor.apana.org.au>,
	"David S . Miller" <davem@davemloft.net>,
	Marc Zyngier <maz@kernel.org>,
	Maximilian Luz <luzmaximilian@gmail.com>,
	Hans de Goede <hdegoede@redhat.com>,
	Mark Gross <markgross@kernel.org>,
	Nathan Chancellor <nathan@kernel.org>,
	Nick Desaulniers <ndesaulniers@google.com>,
	Tom Rix <trix@redhat.com>, Sunil V L <sunilvl@ventanamicro.com>,
	"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>
Subject: [PATCH V5 08/21] RISC-V: ACPI: Cache and retrieve the RINTC structure
Date: Mon,  8 May 2023 17:22:24 +0530	[thread overview]
Message-ID: <20230508115237.216337-9-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com>

RINTC structures in the MADT provide mapping between the hartid
and the CPU. This is required many times even at run time like
cpuinfo. So, instead of parsing the ACPI table every time, cache
the RINTC structures and provide a function to get the correct
RINTC structure for a given cpu.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 arch/riscv/include/asm/acpi.h | 10 ++++++++
 arch/riscv/kernel/acpi.c      | 45 +++++++++++++++++++++++++++++++++++
 arch/riscv/kernel/setup.c     |  4 ++++
 3 files changed, 59 insertions(+)

diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h
index 9be52b6ffae1..6519529c8bdf 100644
--- a/arch/riscv/include/asm/acpi.h
+++ b/arch/riscv/include/asm/acpi.h
@@ -59,6 +59,16 @@ static inline bool acpi_has_cpu_in_madt(void)
 
 static inline void arch_fix_phys_package_id(int num, u32 slot) { }
 
+void acpi_init_rintc_map(void);
+struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu);
+u32 get_acpi_id_for_cpu(int cpu);
+#else
+static inline void acpi_init_rintc_map(void) { }
+static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu)
+{
+	return NULL;
+}
+
 #endif /* CONFIG_ACPI */
 
 #endif /*_ASM_ACPI_H*/
diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c
index 81d448c41714..89e142611c84 100644
--- a/arch/riscv/kernel/acpi.c
+++ b/arch/riscv/kernel/acpi.c
@@ -24,6 +24,51 @@ EXPORT_SYMBOL(acpi_disabled);
 int acpi_pci_disabled = 1;	/* skip ACPI PCI scan and IRQ initialization */
 EXPORT_SYMBOL(acpi_pci_disabled);
 
+static struct acpi_madt_rintc cpu_madt_rintc[NR_CPUS];
+
+static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end)
+{
+	struct acpi_madt_rintc *rintc = (struct acpi_madt_rintc *)header;
+	int cpuid;
+
+	if (!(rintc->flags & ACPI_MADT_ENABLED))
+		return 0;
+
+	cpuid = riscv_hartid_to_cpuid(rintc->hart_id);
+	/*
+	 * When CONFIG_SMP is disabled, mapping won't be created for
+	 * all cpus.
+	 * CPUs more than num_possible_cpus, will be ignored.
+	 */
+	if (cpuid >= 0 && cpuid < num_possible_cpus())
+		cpu_madt_rintc[cpuid] = *rintc;
+
+	return 0;
+}
+
+/*
+ * Instead of parsing (and freeing) the ACPI table, cache
+ * the RINTC structures since they are frequently used
+ * like in  cpuinfo.
+ */
+void __init acpi_init_rintc_map(void)
+{
+	if (acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_madt_rintc, 0) <= 0) {
+		pr_err("No valid RINTC entries exist\n");
+		BUG();
+	}
+}
+
+struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu)
+{
+	return &cpu_madt_rintc[cpu];
+}
+
+u32 get_acpi_id_for_cpu(int cpu)
+{
+	return acpi_cpu_get_madt_rintc(cpu)->uid;
+}
+
 /*
  * __acpi_map_table() will be called before paging_init(), so early_ioremap()
  * or early_memremap() should be called here to for ACPI table mapping.
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index 9fb839074e16..a44c7fcde12f 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -21,6 +21,7 @@
 #include <linux/efi.h>
 #include <linux/crash_dump.h>
 
+#include <asm/acpi.h>
 #include <asm/alternative.h>
 #include <asm/cacheflush.h>
 #include <asm/cpu_ops.h>
@@ -293,6 +294,9 @@ void __init setup_arch(char **cmdline_p)
 	setup_smp();
 #endif
 
+	if (!acpi_disabled)
+		acpi_init_rintc_map();
+
 	riscv_init_cbo_blocksizes();
 	riscv_fill_hwcap();
 	apply_boot_alternatives();
-- 
2.34.1


  parent reply	other threads:[~2023-05-08 11:56 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-08 11:52 [PATCH V5 00/21] Add basic ACPI support for RISC-V Sunil V L
2023-05-08 11:52 ` [PATCH V5 01/21] riscv: move sbi_init() earlier before jump_label_init() Sunil V L
2023-05-08 11:52 ` [PATCH V5 02/21] platform/surface: Disable for RISC-V Sunil V L
2023-05-08 11:52 ` [PATCH V5 03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang Sunil V L
2023-05-09  2:17   ` Herbert Xu
2023-05-10  5:47     ` Sunil V L
2023-05-08 11:52 ` [PATCH V5 04/21] ACPI: tables: Print RINTC information when MADT is parsed Sunil V L
2023-05-08 11:52 ` [PATCH V5 05/21] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Sunil V L
2023-05-08 11:52 ` [PATCH V5 06/21] RISC-V: Add support to build the ACPI core Sunil V L
2023-05-08 11:52 ` [PATCH V5 07/21] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Sunil V L
2023-05-08 11:52 ` Sunil V L [this message]
2023-05-09 17:50   ` [PATCH V5 08/21] RISC-V: ACPI: Cache and retrieve the RINTC structure Conor Dooley
2023-05-10  3:46     ` Sunil V L
2023-05-08 11:52 ` [PATCH V5 09/21] drivers/acpi: RISC-V: Add RHCT related code Sunil V L
2023-05-08 11:52 ` [PATCH V5 10/21] RISC-V: smpboot: Create wrapper setup_smp() Sunil V L
2023-05-08 11:52 ` [PATCH V5 11/21] RISC-V: smpboot: Add ACPI support in setup_smp() Sunil V L
2023-05-08 11:52 ` [PATCH V5 12/21] RISC-V: only iterate over possible CPUs in ISA string parser Sunil V L
2023-05-08 11:52 ` [PATCH V5 13/21] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Sunil V L
2023-05-08 11:52 ` [PATCH V5 14/21] RISC-V: cpu: Enable cpuinfo for ACPI systems Sunil V L
2023-05-08 11:52 ` [PATCH V5 15/21] irqchip/riscv-intc: Add ACPI support Sunil V L
2023-05-08 11:52 ` [PATCH V5 16/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Sunil V L
2023-05-08 11:52 ` [PATCH V5 17/21] clocksource/timer-riscv: Add ACPI support Sunil V L
2023-05-08 11:52 ` [PATCH V5 18/21] RISC-V: time.c: Add ACPI support for time_init() Sunil V L
2023-05-08 11:52 ` [PATCH V5 19/21] RISC-V: Add ACPI initialization in setup_arch() Sunil V L
2023-05-08 11:52 ` [PATCH V5 20/21] RISC-V: Enable ACPI in defconfig Sunil V L
2023-05-08 11:52 ` [PATCH V5 21/21] MAINTAINERS: Add entry for drivers/acpi/riscv Sunil V L

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