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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id 12-20020a05600c020c00b003f4b6bcbd8bsm4941659wmi.31.2023.05.11.09.40.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 09:40:06 -0700 (PDT) Date: Thu, 11 May 2023 18:40:05 +0200 From: Andrew Jones To: Haibo Xu Cc: xiaobo55x@gmail.com, Paolo Bonzini , Jonathan Corbet , Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Shuah Khan , kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH 1/2] riscv: kvm: Add KVM_GET_REG_LIST API support Message-ID: <20230511-d0a207eebb30fc88de875e4f@orel> References: <921fc2e1a91887170e277acb1b52df57480a5736.1683791148.git.haibo1.xu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <921fc2e1a91887170e277acb1b52df57480a5736.1683791148.git.haibo1.xu@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On Thu, May 11, 2023 at 05:22:48PM +0800, Haibo Xu wrote: > KVM_GET_REG_LIST API will return all registers that are available to > KVM_GET/SET_ONE_REG APIs. It's very useful to identify some platform > regression issue during VM migration. > > Since this API was already supported on arm64, it'd be straightforward > to enable it on riscv with similar code structure. > > Signed-off-by: Haibo Xu > --- > Documentation/virt/kvm/api.rst | 2 +- > arch/riscv/kvm/vcpu.c | 346 +++++++++++++++++++++++++++++++++ > 2 files changed, 347 insertions(+), 1 deletion(-) > > diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst > index add067793b90..280e89abd004 100644 > --- a/Documentation/virt/kvm/api.rst > +++ b/Documentation/virt/kvm/api.rst > @@ -3499,7 +3499,7 @@ VCPU matching underlying host. > --------------------- > > :Capability: basic > -:Architectures: arm64, mips > +:Architectures: arm64, mips, riscv > :Type: vcpu ioctl > :Parameters: struct kvm_reg_list (in/out) > :Returns: 0 on success; -1 on error > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c > index 8bd9f2a8a0b9..fb8834e4fa15 100644 > --- a/arch/riscv/kvm/vcpu.c > +++ b/arch/riscv/kvm/vcpu.c > @@ -657,6 +657,334 @@ static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu, > return 0; > } > > +static inline unsigned long num_config_regs(void) > +{ > + return sizeof(struct kvm_riscv_config) / sizeof(unsigned long); We can't assume all config registers are present. For example, zicbom and zicboz block size registers are only present when their respective extensions are available. Thanks, drew