From: Peter Zijlstra <peterz@infradead.org>
To: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
Josh Poimboeuf <jpoimboe@kernel.org>,
Andy Lutomirski <luto@kernel.org>,
Jonathan Corbet <corbet@lwn.net>,
Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>,
tony.luck@intel.com, ak@linux.intel.com,
tim.c.chen@linux.intel.com, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
Alyssa Milburn <alyssa.milburn@linux.intel.com>,
Daniel Sneddon <daniel.sneddon@linux.intel.com>,
antonio.gomez.iglesias@linux.intel.com,
Alyssa Milburn <alyssa.milburn@intel.com>
Subject: Re: [PATCH v2 1/6] x86/bugs: Add asm helpers for executing VERW
Date: Wed, 25 Oct 2023 08:56:10 +0200 [thread overview]
Message-ID: <20231025065610.GA31201@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <20231025040029.uglv4dwmlnfhcjde@desk>
On Tue, Oct 24, 2023 at 09:00:29PM -0700, Pawan Gupta wrote:
> config1: mitigations=on, 32-bit mode, post-boot
>
> entry_SYSENTER_32:
> ...
> 0xc1a3748e <+222>: pop %eax
> 0xc1a3748f <+223>: verw 0xc1a38240
> 0xc1a37496 <+230>: sti
> 0xc1a37497 <+231>: sysexit
>
> ---------------------------------------------
>
> config2: mitigations=off, 32-bit mode, post-boot
>
> entry_SYSENTER_32:
> ...
> 0xc1a3748e <+222>: pop %eax
> 0xc1a3748f <+223>: lea 0x0(%esi,%eiz,1),%esi <---- Doesn't look right
> 0xc1a37496 <+230>: sti
> 0xc1a37497 <+231>: sysexit
>
> ---------------------------------------------
>
> config3: 32-bit mode, pre-boot objdump
>
> entry_SYSENTER_32:
> ...
> c8e: 58 pop %eax
> c8f: 90 nop
> c90: 90 nop
> c91: 90 nop
> c92: 90 nop
> c93: 90 nop
> c94: 90 nop
> c95: 90 nop
> c96: fb sti
> c97: 0f 35 sysexit
>
If you look at arch/x86/include/asm/nops.h, you'll find (for 32bit):
* 7: leal 0x0(%esi,%eiz,1),%esi
Which reads as:
load-effective-address of %esi[0] into %esi
which is, of course, just %esi.
You can also get this from GAS using:
.nops 7
which results in:
0: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
It is basically abusing bizarro x86 instruction encoding rules to create
a 7 byte nop without using NOPL. If you really want to know, volume 2
of the SDM has a ton of stuff on instruction encoding, also the interweb
:-)
next prev parent reply other threads:[~2023-10-25 6:56 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-24 8:08 [PATCH v2 0/6] Delay VERW Pawan Gupta
2023-10-24 8:08 ` [PATCH v2 1/6] x86/bugs: Add asm helpers for executing VERW Pawan Gupta
2023-10-24 10:36 ` Peter Zijlstra
2023-10-24 16:35 ` Pawan Gupta
2023-10-24 16:36 ` Peter Zijlstra
2023-10-24 16:45 ` Pawan Gupta
2023-10-24 17:02 ` Peter Zijlstra
2023-10-24 17:30 ` Pawan Gupta
2023-10-24 18:27 ` H. Peter Anvin
2023-10-24 18:49 ` Luck, Tony
2023-10-24 19:14 ` H. Peter Anvin
2023-10-24 19:40 ` Luck, Tony
2023-10-24 20:30 ` H. Peter Anvin
2023-10-24 22:30 ` Peter Zijlstra
2023-10-24 22:28 ` Peter Zijlstra
2023-10-25 4:00 ` Pawan Gupta
2023-10-25 6:56 ` Peter Zijlstra [this message]
2023-10-25 15:06 ` Pawan Gupta
2023-10-25 6:58 ` Peter Zijlstra
2023-10-25 15:10 ` Pawan Gupta
2023-10-24 8:08 ` [PATCH v2 2/6] x86/entry_64: Add VERW just before userspace transition Pawan Gupta
2023-10-24 8:08 ` [PATCH v2 3/6] x86/entry_32: " Pawan Gupta
2023-10-24 8:08 ` [PATCH v2 4/6] x86/bugs: Use ALTERNATIVE() instead of mds_user_clear static key Pawan Gupta
2023-10-25 22:08 ` kernel test robot
2023-10-24 8:08 ` [PATCH v2 5/6] KVM: VMX: Use BT+JNC, i.e. EFLAGS.CF to select VMRESUME vs. VMLAUNCH Pawan Gupta
2023-10-25 8:15 ` Nikolay Borisov
2023-10-24 8:08 ` [PATCH v2 6/6] KVM: VMX: Move VERW closer to VMentry for MDS mitigation Pawan Gupta
2023-10-25 7:47 ` Chao Gao
2023-10-25 15:15 ` Pawan Gupta
2023-10-24 12:26 ` [PATCH v2 0/6] Delay VERW Matthew Wilcox
2023-10-24 17:01 ` Pawan Gupta
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