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From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: "Atish Patra" <atishp@rivosinc.com>,
	"Adrian Hunter" <adrian.hunter@intel.com>,
	"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
	"Alexandre Ghiti" <alexghiti@rivosinc.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Arnaldo Carvalho de Melo" <acme@kernel.org>,
	"Atish Patra" <atishp@atishpatra.org>,
	"Christian Brauner" <brauner@kernel.org>,
	"Clément Léger" <cleger@rivosinc.com>,
	"Conor Dooley" <conor@kernel.org>,
	devicetree@vger.kernel.org, "Evan Green" <evan@rivosinc.com>,
	"Guo Ren" <guoren@kernel.org>, "Heiko Stuebner" <heiko@sntech.de>,
	"Ian Rogers" <irogers@google.com>,
	"Ingo Molnar" <mingo@redhat.com>,
	"James Clark" <james.clark@arm.com>,
	"Jing Zhang" <renyu.zj@linux.alibaba.com>,
	"Jiri Olsa" <jolsa@kernel.org>,
	"Ji Sheng Teoh" <jisheng.teoh@starfivetech.com>,
	"John Garry" <john.g.garry@oracle.com>,
	"Jonathan Corbet" <corbet@lwn.net>,
	"Kan Liang" <kan.liang@linux.intel.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
	"Ley Foon Tan" <leyfoon.tan@starfivetech.com>,
	linux-doc@vger.kernel.org, linux-perf-users@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	"Mark Rutland" <mark.rutland@arm.com>,
	"Namhyung Kim" <namhyung@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Peter Zijlstra" <peterz@infradead.org>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Weilin Wang" <weilin.wang@intel.com>,
	"Will Deacon" <will@kernel.org>,
	kaiwenxue1@gmail.com, "Yang Jihong" <yangjihong1@huawei.com>
Subject: [PATCH RFC 02/20] RISC-V: Add Sxcsrind ISA extension CSR definitions
Date: Fri, 16 Feb 2024 16:57:20 -0800	[thread overview]
Message-ID: <20240217005738.3744121-3-atishp@rivosinc.com> (raw)
In-Reply-To: <20240217005738.3744121-1-atishp@rivosinc.com>

From: Kaiwen Xue <kaiwenx@rivosinc.com>

This adds definitions of new CSRs and bits defined in Sxcsrind ISA
extension. These CSR enables indirect accesses mechanism to access
any CSRs in M-, S-, and VS-mode. The range of the select values
and ireg will be define by the ISA extension using Sxcsrind extension.

Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/include/asm/csr.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 510014051f5d..0a54856fd807 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -302,6 +302,12 @@
 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
 #define CSR_SISELECT		0x150
 #define CSR_SIREG		0x151
+/* Supervisor-Level Window to Indirectly Accessed Registers (Sxcsrind) */
+#define CSR_SIREG2		0x152
+#define CSR_SIREG3		0x153
+#define CSR_SIREG4		0x155
+#define CSR_SIREG5		0x156
+#define CSR_SIREG6		0x157
 
 /* Supervisor-Level Interrupts (AIA) */
 #define CSR_STOPEI		0x15c
@@ -349,6 +355,14 @@
 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
 #define CSR_VSISELECT		0x250
 #define CSR_VSIREG		0x251
+/*
+ * VS-Level Window to Indirectly Accessed Registers (H-extension with Sxcsrind)
+ */
+#define CSR_VSIREG2		0x252
+#define CSR_VSIREG3		0x253
+#define CSR_VSIREG4		0x255
+#define CSR_VSIREG5		0x256
+#define CSR_VISREG6		0x257
 
 /* VS-Level Interrupts (H-extension with AIA) */
 #define CSR_VSTOPEI		0x25c
@@ -389,6 +403,12 @@
 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
 #define CSR_MISELECT		0x350
 #define CSR_MIREG		0x351
+/* Machine-Level Window to Indrecitly Accessed Registers (Sxcsrind) */
+#define CSR_MIREG2		0x352
+#define CSR_MIREG3		0x353
+#define CSR_MIREG4		0x355
+#define CSR_MIREG5		0x356
+#define CSR_MIREG6		0x357
 
 /* Machine-Level Interrupts (AIA) */
 #define CSR_MTOPEI		0x35c
-- 
2.34.1


  parent reply	other threads:[~2024-02-17  0:58 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-17  0:57 [PATCH RFC 00/20] Add Counter delegation ISA extension support Atish Patra
2024-02-17  0:57 ` [PATCH RFC 01/20] perf pmu-events: Add functions in jevent.py to parse counter and event info for hardware aware grouping Atish Patra
2024-02-17  0:57 ` Atish Patra [this message]
2024-02-17  0:57 ` [PATCH RFC 03/20] RISC-V: Add Sxcsrind ISA extension definition and parsing Atish Patra
2024-02-17  0:57 ` [PATCH RFC 04/20] dt-bindings: riscv: add Sxcsrind ISA extension description Atish Patra
2024-02-18 12:47   ` Conor Dooley
2024-02-17  0:57 ` [PATCH RFC 05/20] RISC-V: Define indirect CSR access helpers Atish Patra
2024-02-17  0:57 ` [PATCH RFC 06/20] RISC-V: Add Sscfg extension CSR definition Atish Patra
2024-02-17  0:57 ` [PATCH RFC 07/20] RISC-V: Add Ssccfg ISA extension definition and parsing Atish Patra
2024-02-17  0:57 ` [PATCH RFC 08/20] dt-bindings: riscv: add Ssccfg ISA extension description Atish Patra
2024-02-17  2:33   ` Rob Herring
2024-02-17  0:57 ` [PATCH RFC 09/20] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2024-02-18 12:50   ` Conor Dooley
2024-02-17  0:57 ` [PATCH RFC 10/20] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2024-02-17  2:33   ` Rob Herring
2024-02-17  0:57 ` [PATCH RFC 11/20] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2024-02-17  0:57 ` [PATCH RFC 12/20] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2024-02-17  0:57 ` [PATCH RFC 13/20] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2024-02-17  0:57 ` [PATCH RFC 14/20] RISC-V: perf: Use config2 for event to counter mapping Atish Patra
2024-02-17  0:57 ` [PATCH RFC 15/20] tools/perf: Add arch hooks to override perf standard events Atish Patra
2024-02-17  0:57 ` [PATCH RFC 16/20] tools/perf: Pass the Counter constraint values in the pmu events Atish Patra
2024-02-17  0:57 ` [PATCH RFC 17/20] perf: Add json file for virt machine supported events Atish Patra
2024-02-17  0:57 ` [PATCH RFC 18/20] tools arch uapi: Sync the uinstd.h header file for RISC-V Atish Patra
2024-02-17  0:57 ` [PATCH RFC 19/20] RISC-V: Add hwprobe support for Counter delegation extensions Atish Patra
2024-02-17  0:57 ` [PATCH RFC 20/20] tools/perf: Detect if platform supports counter delegation Atish Patra
2024-02-17 20:28 ` [PATCH RFC 00/20] Add Counter delegation ISA extension support Ian Rogers
2024-02-29  1:25   ` Atish Patra

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