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From: kernel test robot <lkp@intel.com>
To: "Charlie Jenkins" <charlie@rivosinc.com>,
	"Conor Dooley" <conor@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Guo Ren" <guoren@kernel.org>, "Chen-Yu Tsai" <wens@csie.org>,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	"Samuel Holland" <samuel@sholland.org>,
	"Evan Green" <evan@rivosinc.com>,
	"Clément Léger" <cleger@rivosinc.com>,
	"Jonathan Corbet" <corbet@lwn.net>,
	"Shuah Khan" <skhan@linuxfoundation.org>
Cc: oe-kbuild-all@lists.linux.dev, linux-riscv@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
	linux-kselftest@vger.kernel.org,
	Charlie Jenkins <charlie@rivosinc.com>
Subject: Re: [PATCH 06/19] riscv: Extend cpufeature.c to detect vendor extensions
Date: Sun, 14 Apr 2024 06:10:50 +0800	[thread overview]
Message-ID: <202404140621.x9B02eF8-lkp@intel.com> (raw)
In-Reply-To: <20240411-dev-charlie-support_thead_vector_6_9-v1-6-4af9815ec746@rivosinc.com>

Hi Charlie,

kernel test robot noticed the following build errors:

[auto build test ERROR on 4cece764965020c22cff7665b18a012006359095]

url:    https://github.com/intel-lab-lkp/linux/commits/Charlie-Jenkins/dt-bindings-riscv-Add-vendorid-and-archid/20240412-121709
base:   4cece764965020c22cff7665b18a012006359095
patch link:    https://lore.kernel.org/r/20240411-dev-charlie-support_thead_vector_6_9-v1-6-4af9815ec746%40rivosinc.com
patch subject: [PATCH 06/19] riscv: Extend cpufeature.c to detect vendor extensions
config: riscv-randconfig-r133-20240413 (https://download.01.org/0day-ci/archive/20240414/202404140621.x9B02eF8-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
reproduce: (https://download.01.org/0day-ci/archive/20240414/202404140621.x9B02eF8-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202404140621.x9B02eF8-lkp@intel.com/

All errors (new ones prefixed by >>):

>> arch/riscv/kernel/cpufeature.c:395:4: error: expected expression
     395 |                         bool found;
         |                         ^
>> arch/riscv/kernel/cpufeature.c:397:4: error: use of undeclared identifier 'found'
     397 |                         found = get_isa_vendor_ext(vendorid,
         |                         ^
   arch/riscv/kernel/cpufeature.c:402:9: error: use of undeclared identifier 'found'
     402 |                         if (!found) {
         |                              ^
   3 errors generated.


vim +395 arch/riscv/kernel/cpufeature.c

   370	
   371	static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct riscv_isainfo *isainfo,
   372						struct riscv_isainfo *isavendorinfo, unsigned long vendorid,
   373						unsigned long *isa2hwcap, const char *isa)
   374	{
   375		/*
   376		 * For all possible cpus, we have already validated in
   377		 * the boot process that they at least contain "rv" and
   378		 * whichever of "32"/"64" this kernel supports, and so this
   379		 * section can be skipped.
   380		 */
   381		isa += 4;
   382	
   383		while (*isa) {
   384			const char *ext = isa++;
   385			const char *ext_end = isa;
   386			bool ext_long = false, ext_err = false;
   387			struct riscv_isainfo *selected_isainfo = isainfo;
   388			const struct riscv_isa_ext_data *selected_riscv_isa_ext = riscv_isa_ext;
   389			size_t selected_riscv_isa_ext_count = riscv_isa_ext_count;
   390			unsigned int id_offset = 0;
   391	
   392			switch (*ext) {
   393			case 'x':
   394			case 'X':
 > 395				bool found;
   396	
 > 397				found = get_isa_vendor_ext(vendorid,
   398							   &selected_riscv_isa_ext,
   399							   &selected_riscv_isa_ext_count);
   400				selected_isainfo = isavendorinfo;
   401				id_offset = RISCV_ISA_VENDOR_EXT_BASE;
   402				if (!found) {
   403					pr_warn("No associated vendor extensions with vendor id: %lx\n",
   404						vendorid);
   405					for (; *isa && *isa != '_'; ++isa)
   406						;
   407					ext_err = true;
   408					break;
   409				}
   410				fallthrough;
   411			case 's':
   412				/*
   413				 * Workaround for invalid single-letter 's' & 'u' (QEMU).
   414				 * No need to set the bit in riscv_isa as 's' & 'u' are
   415				 * not valid ISA extensions. It works unless the first
   416				 * multi-letter extension in the ISA string begins with
   417				 * "Su" and is not prefixed with an underscore.
   418				 */
   419				if (ext[-1] != '_' && ext[1] == 'u') {
   420					++isa;
   421					ext_err = true;
   422					break;
   423				}
   424				fallthrough;
   425			case 'S':
   426			case 'z':
   427			case 'Z':
   428				/*
   429				 * Before attempting to parse the extension itself, we find its end.
   430				 * As multi-letter extensions must be split from other multi-letter
   431				 * extensions with an "_", the end of a multi-letter extension will
   432				 * either be the null character or the "_" at the start of the next
   433				 * multi-letter extension.
   434				 *
   435				 * Next, as the extensions version is currently ignored, we
   436				 * eliminate that portion. This is done by parsing backwards from
   437				 * the end of the extension, removing any numbers. This may be a
   438				 * major or minor number however, so the process is repeated if a
   439				 * minor number was found.
   440				 *
   441				 * ext_end is intended to represent the first character *after* the
   442				 * name portion of an extension, but will be decremented to the last
   443				 * character itself while eliminating the extensions version number.
   444				 * A simple re-increment solves this problem.
   445				 */
   446				ext_long = true;
   447				for (; *isa && *isa != '_'; ++isa)
   448					if (unlikely(!isalnum(*isa)))
   449						ext_err = true;
   450	
   451				ext_end = isa;
   452				if (unlikely(ext_err))
   453					break;
   454	
   455				if (!isdigit(ext_end[-1]))
   456					break;
   457	
   458				while (isdigit(*--ext_end))
   459					;
   460	
   461				if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) {
   462					++ext_end;
   463					break;
   464				}
   465	
   466				while (isdigit(*--ext_end))
   467					;
   468	
   469				++ext_end;
   470				break;
   471			default:
   472				/*
   473				 * Things are a little easier for single-letter extensions, as they
   474				 * are parsed forwards.
   475				 *
   476				 * After checking that our starting position is valid, we need to
   477				 * ensure that, when isa was incremented at the start of the loop,
   478				 * that it arrived at the start of the next extension.
   479				 *
   480				 * If we are already on a non-digit, there is nothing to do. Either
   481				 * we have a multi-letter extension's _, or the start of an
   482				 * extension.
   483				 *
   484				 * Otherwise we have found the current extension's major version
   485				 * number. Parse past it, and a subsequent p/minor version number
   486				 * if present. The `p` extension must not appear immediately after
   487				 * a number, so there is no fear of missing it.
   488				 *
   489				 */
   490				if (unlikely(!isalpha(*ext))) {
   491					ext_err = true;
   492					break;
   493				}
   494	
   495				if (!isdigit(*isa))
   496					break;
   497	
   498				while (isdigit(*++isa))
   499					;
   500	
   501				if (tolower(*isa) != 'p')
   502					break;
   503	
   504				if (!isdigit(*++isa)) {
   505					--isa;
   506					break;
   507				}
   508	
   509				while (isdigit(*++isa))
   510					;
   511	
   512				break;
   513			}
   514	
   515			/*
   516			 * The parser expects that at the start of an iteration isa points to the
   517			 * first character of the next extension. As we stop parsing an extension
   518			 * on meeting a non-alphanumeric character, an extra increment is needed
   519			 * where the succeeding extension is a multi-letter prefixed with an "_".
   520			 */
   521			if (*isa == '_')
   522				++isa;
   523	
   524			if (unlikely(ext_err))
   525				continue;
   526			if (!ext_long) {
   527				int nr = tolower(*ext) - 'a';
   528	
   529				if (riscv_isa_extension_check(nr)) {
   530					*this_hwcap |= isa2hwcap[nr];
   531					set_bit(nr, isainfo->isa);
   532				}
   533			} else {
   534				for (int i = 0; i < selected_riscv_isa_ext_count; i++)
   535					match_isa_ext(&selected_riscv_isa_ext[i], ext,
   536						      ext_end, selected_isainfo,
   537						      id_offset);
   538			}
   539		}
   540	}
   541	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

  parent reply	other threads:[~2024-04-13 22:11 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-12  4:11 [PATCH 00/19] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-04-12  4:11 ` [PATCH 01/19] dt-bindings: riscv: Add vendorid and archid Charlie Jenkins
2024-04-12  9:57   ` Conor Dooley
2024-04-12  4:11 ` [PATCH 02/19] riscv: cpufeature: Fix thead vector hwcap removal Charlie Jenkins
2024-04-12 10:25   ` Conor Dooley
2024-04-12 17:04     ` Evan Green
2024-04-12 18:38       ` Conor Dooley
2024-04-12 18:46         ` Charlie Jenkins
2024-04-12 19:26           ` Conor Dooley
2024-04-12 20:34             ` Charlie Jenkins
2024-04-12 20:42               ` Conor Dooley
2024-04-12 17:12     ` Charlie Jenkins
2024-04-12 18:47       ` Conor Dooley
2024-04-12 20:48         ` Charlie Jenkins
2024-04-12 21:27           ` Conor Dooley
2024-04-12 21:31             ` Charlie Jenkins
2024-04-12 23:40               ` Conor Dooley
2024-04-16  3:34                 ` Charlie Jenkins
2024-04-16  7:36                   ` Conor Dooley
2024-04-17  4:25                     ` Charlie Jenkins
2024-04-17 16:02                       ` Evan Green
2024-04-17 22:02                         ` Charlie Jenkins
2024-04-12  4:11 ` [PATCH 03/19] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-04-12 10:27   ` Conor Dooley
2024-04-12 17:13     ` Charlie Jenkins
2024-04-12  4:11 ` [PATCH 04/19] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-04-12  4:11 ` [PATCH 05/19] riscv: Fix extension subset checking Charlie Jenkins
2024-04-12 11:25   ` Conor Dooley
2024-04-12  4:11 ` [PATCH 06/19] riscv: Extend cpufeature.c to detect vendor extensions Charlie Jenkins
2024-04-12 12:30   ` Conor Dooley
2024-04-12 16:58     ` Charlie Jenkins
2024-04-12 18:59       ` Conor Dooley
2024-04-12 14:44   ` kernel test robot
2024-04-13 22:10   ` kernel test robot [this message]
2024-04-12  4:11 ` [PATCH 07/19] riscv: Optimize riscv_cpu_isa_extension_(un)likely() Charlie Jenkins
2024-04-12 10:40   ` Conor Dooley
2024-04-12 17:34     ` Charlie Jenkins
2024-04-12 20:33       ` Conor Dooley
2024-04-12  4:11 ` [PATCH 08/19] riscv: Introduce vendor variants of extension helpers Charlie Jenkins
2024-04-12 11:49   ` Conor Dooley
2024-04-12 17:43     ` Charlie Jenkins
2024-04-12 20:40       ` Conor Dooley
2024-04-12 21:03         ` Charlie Jenkins
2024-04-12 21:34           ` Conor Dooley
2024-04-12 21:56             ` Charlie Jenkins
2024-04-12  4:11 ` [PATCH 09/19] riscv: uaccess: Add alternative for xtheadvector uaccess Charlie Jenkins
2024-04-12  4:11 ` [PATCH 10/19] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-04-12 11:27   ` Conor Dooley
2024-04-12 18:22     ` Charlie Jenkins
2024-04-12  4:11 ` [PATCH 11/19] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Charlie Jenkins
2024-04-12  4:11 ` [PATCH 12/19] riscv: Create xtheadvector file Charlie Jenkins
2024-04-12 11:30   ` Conor Dooley
2024-04-12 18:24     ` Charlie Jenkins
2024-04-12 19:00       ` Conor Dooley
2024-04-12 20:53         ` Charlie Jenkins
2024-04-12  4:11 ` [PATCH 13/19] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-04-12  4:11 ` [PATCH 14/19] riscv: hwprobe: Disambiguate vector and xtheadvector in hwprobe Charlie Jenkins
2024-04-12 11:34   ` Conor Dooley
2024-04-12 17:04     ` Evan Green
2024-04-12 18:22       ` Charlie Jenkins
2024-04-12 22:08         ` Evan Green
2024-04-12 22:37           ` Charlie Jenkins
2024-04-12  4:11 ` [PATCH 15/19] riscv: hwcap: Add v to hwcap if xtheadvector enabled Charlie Jenkins
2024-04-12 11:37   ` Conor Dooley
2024-04-12 18:26     ` Charlie Jenkins
2024-04-12  4:11 ` [PATCH 16/19] riscv: hwprobe: Add vendor extension probing Charlie Jenkins
2024-04-12 11:39   ` Conor Dooley
2024-04-12 17:05   ` Evan Green
2024-04-12 18:16     ` Charlie Jenkins
2024-04-12 19:07       ` Evan Green
2024-04-12 20:20         ` Charlie Jenkins
2024-04-12 21:43           ` Evan Green
2024-04-12 22:21             ` Charlie Jenkins
2024-04-12 22:50               ` Evan Green
2024-04-12 23:12                 ` Charlie Jenkins
2024-04-12  4:11 ` [PATCH 17/19] riscv: hwprobe: Document vendor extensions and xtheadvector extension Charlie Jenkins
2024-04-12  4:11 ` [PATCH 18/19] selftests: riscv: Fix vector tests Charlie Jenkins
2024-04-12  4:11 ` [PATCH 19/19] selftests: riscv: Support xtheadvector in " Charlie Jenkins

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