From: Conor Dooley <conor@kernel.org>
To: Evan Green <evan@rivosinc.com>
Cc: "Palmer Dabbelt" <palmer@dabbelt.com>,
"Yangyu Chen" <cyy@cyyself.name>,
"Charlie Jenkins" <charlie@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Andy Chiu" <andy.chiu@sifive.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Costa Shulyupin" <costa.shul@redhat.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 1/2] RISC-V: hwprobe: Add MISALIGNED_PERF key
Date: Wed, 26 Jun 2024 15:36:35 +0100 [thread overview]
Message-ID: <20240626-aide-nickname-1ef5fef000fb@spud> (raw)
In-Reply-To: <20240625165121.2160354-2-evan@rivosinc.com>
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On Tue, Jun 25, 2024 at 09:51:20AM -0700, Evan Green wrote:
> RISCV_HWPROBE_KEY_CPUPERF_0 was mistakenly flagged as a bitmask in
> hwprobe_key_is_bitmask(), when in reality it was an enum value. This
> causes problems when used in conjunction with RISCV_HWPROBE_WHICH_CPUS,
> since SLOW, FAST, and EMULATED have values whose bits overlap with
> each other. If the caller asked for the set of CPUs that was SLOW or
> EMULATED, the returned set would also include CPUs that were FAST.
>
> Introduce a new hwprobe key, RISCV_HWPROBE_KEY_MISALIGNED_PERF, which
> returns the same values in response to a direct query (with no flags),
> but is properly handled as an enumerated value. As a result, SLOW,
> FAST, and EMULATED are all correctly treated as distinct values under
> the new key when queried with the WHICH_CPUS flag.
>
> Leave the old key in place to avoid disturbing applications which may
> have already come to rely on the key, with or without its broken
> behavior with respect to the WHICH_CPUS flag.
>
> Fixes: e178bf146e4b ("RISC-V: hwprobe: Introduce which-cpus flag")
> Signed-off-by: Evan Green <evan@rivosinc.com>
> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>
> ---
>
> Changes in v2:
> - Clarified the distinction of slow and fast refers to misaligned word
> accesses. Previously it just said misaligned accesses, leaving it
> ambiguous as to which type of access was measured.
I think if we are gonna be specific, we should be exactly specific as to
what we have tested and say 32-bit if that's what we're probing/testing
with. That'd be consistent with jesse's proposed wording for vector.
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next prev parent reply other threads:[~2024-06-26 14:36 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-25 16:51 [PATCH v2 0/2] RISC-V: hwprobe: Misaligned scalar perf fix and rename Evan Green
2024-06-25 16:51 ` [PATCH v2 1/2] RISC-V: hwprobe: Add MISALIGNED_PERF key Evan Green
2024-06-26 14:36 ` Conor Dooley [this message]
2024-06-26 15:55 ` Evan Green
2024-06-25 16:51 ` [PATCH v2 2/2] RISC-V: hwprobe: Add SCALAR to misaligned perf defines Evan Green
2024-06-25 18:33 ` Charlie Jenkins
2024-06-25 18:35 ` Conor Dooley
2024-06-25 19:08 ` Evan Green
2024-06-26 14:34 ` Conor Dooley
2024-06-26 15:44 ` Evan Green
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