From: Conor Dooley <conor@kernel.org>
To: Jesse Taube <jesse@rivosinc.com>
Cc: linux-riscv@lists.infradead.org,
"Jonathan Corbet" <corbet@lwn.net>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Clément Léger" <cleger@rivosinc.com>,
"Evan Green" <evan@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Charlie Jenkins" <charlie@rivosinc.com>,
"Xiao Wang" <xiao.w.wang@intel.com>,
"Andy Chiu" <andy.chiu@sifive.com>,
"Eric Biggers" <ebiggers@google.com>,
"Greentime Hu" <greentime.hu@sifive.com>,
"Björn Töpel" <bjorn@rivosinc.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Costa Shulyupin" <costa.shul@redhat.com>,
"Andrew Morton" <akpm@linux-foundation.org>,
"Baoquan He" <bhe@redhat.com>,
"Anup Patel" <apatel@ventanamicro.com>,
"Zong Li" <zong.li@sifive.com>,
"Sami Tolvanen" <samitolvanen@google.com>,
"Ben Dooks" <ben.dooks@codethink.co.uk>,
"Alexandre Ghiti" <alexghiti@rivosinc.com>,
"Gustavo A. R. Silva" <gustavoars@kernel.org>,
"Erick Archer" <erick.archer@gmx.com>,
"Joel Granados" <j.granados@samsung.com>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v3 4/8] RISC-V: Check Zicclsm to set unaligned access speed
Date: Wed, 26 Jun 2024 15:39:14 +0100 [thread overview]
Message-ID: <20240626-march-abreast-83414e844250@spud> (raw)
In-Reply-To: <20240625005001.37901-5-jesse@rivosinc.com>
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On Mon, Jun 24, 2024 at 08:49:57PM -0400, Jesse Taube wrote:
> Check for Zicclsm before checking for unaligned access speed. This will
> greatly reduce the boot up time as finding the access speed is no longer
> necessary.
>
> Signed-off-by: Jesse Taube <jesse@rivosinc.com>
> ---
> V2 -> V3:
> - New patch split from previous patch
> ---
> arch/riscv/kernel/unaligned_access_speed.c | 26 ++++++++++++++--------
> 1 file changed, 17 insertions(+), 9 deletions(-)
>
> diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c
> index a9a6bcb02acf..329fd289b5c8 100644
> --- a/arch/riscv/kernel/unaligned_access_speed.c
> +++ b/arch/riscv/kernel/unaligned_access_speed.c
> @@ -259,23 +259,31 @@ static int check_unaligned_access_speed_all_cpus(void)
> kfree(bufs);
> return 0;
> }
> +#else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */
> +static int check_unaligned_access_speed_all_cpus(void)
> +{
> + return 0;
> +}
> +#endif
>
> static int check_unaligned_access_all_cpus(void)
> {
> - bool all_cpus_emulated = check_unaligned_access_emulated_all_cpus();
> + bool all_cpus_emulated;
> + int cpu;
> +
> + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICCLSM)) {
> + for_each_online_cpu(cpu) {
> + per_cpu(misaligned_access_speed, cpu) = RISCV_HWPROBE_MISALIGNED_FAST;
- const: zicclsm
description:
The standard Zicclsm extension for misaligned support for all regular
load and store instructions (including scalar and vector) but not AMOs
or other specialized forms of memory access. Defined in the
RISC-V RVA Profiles Specification.
Doesn't, unfortunately, say anywhere there that they're actually fast :(
Thanks,
Conor.
> + }
> + return 0;
> + }
> +
> + all_cpus_emulated = check_unaligned_access_emulated_all_cpus();
>
> if (!all_cpus_emulated)
> return check_unaligned_access_speed_all_cpus();
>
> return 0;
> }
> -#else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */
> -static int check_unaligned_access_all_cpus(void)
> -{
> - check_unaligned_access_emulated_all_cpus();
> -
> - return 0;
> -}
> -#endif
>
> arch_initcall(check_unaligned_access_all_cpus);
> --
> 2.45.2
>
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next prev parent reply other threads:[~2024-06-26 14:39 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-25 0:49 [PATCH v3 0/8] RISC-V: Detect and report speed of unaligned vector accesses Jesse Taube
2024-06-25 0:49 ` [PATCH v3 1/8] RISC-V: Add Zicclsm to cpufeature and hwprobe Jesse Taube
2024-06-26 14:41 ` Conor Dooley
2024-06-25 0:49 ` [PATCH v3 2/8] dt-bindings: riscv: Add Zicclsm ISA extension description Jesse Taube
2024-06-25 0:49 ` [PATCH v3 3/8] RISC-V: Check scalar unaligned access on all CPUs Jesse Taube
2024-07-10 15:55 ` Evan Green
2024-07-11 20:25 ` Jesse Taube
2024-06-25 0:49 ` [PATCH v3 4/8] RISC-V: Check Zicclsm to set unaligned access speed Jesse Taube
2024-06-26 14:39 ` Conor Dooley [this message]
2024-06-27 21:20 ` Charlie Jenkins
2024-07-01 7:15 ` Clément Léger
2024-07-01 13:58 ` Conor Dooley
2024-07-01 14:20 ` Clément Léger
2024-07-02 22:22 ` Charlie Jenkins
2024-07-03 7:13 ` Clément Léger
2024-07-03 21:47 ` Jesse Taube
2024-06-25 0:49 ` [PATCH v3 5/8] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED Jesse Taube
2024-06-26 14:39 ` Conor Dooley
2024-06-25 0:49 ` [PATCH v3 6/8] RISC-V: Detect unaligned vector accesses supported Jesse Taube
2024-07-01 15:13 ` Samuel Holland
2024-06-25 0:50 ` [PATCH v3 7/8] RISC-V: Report vector unaligned access speed hwprobe Jesse Taube
2024-07-01 22:51 ` Evan Green
2024-07-11 20:35 ` Jesse Taube
2024-06-25 0:50 ` [PATCH v3 8/8] RISC-V: hwprobe: Document unaligned vector perf key Jesse Taube
2024-06-26 14:37 ` Conor Dooley
2024-07-01 22:55 ` Evan Green
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