* [PATCH v3] RISC-V: Provide the frequency of time CSR via hwprobe
@ 2024-06-22 2:55 Yunhui Cui
2024-06-25 2:08 ` yunhui cui
2024-06-26 13:01 ` Conor Dooley
0 siblings, 2 replies; 4+ messages in thread
From: Yunhui Cui @ 2024-06-22 2:55 UTC (permalink / raw)
To: jesse, jrtc27, corbet, paul.walmsley, palmer, aou, cleger, evan,
conor.dooley, cuiyunhui, costa.shul, andy.chiu, samitolvanen,
linux-doc, linux-riscv, linux-kernel
Cc: Palmer Dabbelt, Anup Patel
From: Palmer Dabbelt <palmer@rivosinc.com>
A handful of user-visible behavior is based on the frequency of the
time CSR.
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
Documentation/arch/riscv/hwprobe.rst | 2 ++
arch/riscv/include/asm/hwprobe.h | 2 +-
arch/riscv/include/uapi/asm/hwprobe.h | 1 +
arch/riscv/kernel/sys_hwprobe.c | 5 +++++
4 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index df5045103e73..ec3c99474ed7 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -233,3 +233,5 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
represents the size of the Zicboz block in bytes.
+
+* :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`.
diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
index 150a9877b0af..ef01c182af2b 100644
--- a/arch/riscv/include/asm/hwprobe.h
+++ b/arch/riscv/include/asm/hwprobe.h
@@ -8,7 +8,7 @@
#include <uapi/asm/hwprobe.h>
-#define RISCV_HWPROBE_MAX_KEY 7
+#define RISCV_HWPROBE_MAX_KEY 8
static inline bool riscv_hwprobe_key_is_valid(__s64 key)
{
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 2fb8a8185e7a..5053a9b18710 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -74,6 +74,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
#define RISCV_HWPROBE_KEY_MISALIGNED_PERF 7
+#define RISCV_HWPROBE_KEY_TIME_CSR_FREQ 8
/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
/* Flags */
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index e4ec9166339f..3d47edc04a3f 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -8,6 +8,7 @@
#include <asm/cacheflush.h>
#include <asm/cpufeature.h>
#include <asm/hwprobe.h>
+#include <asm/delay.h>
#include <asm/sbi.h>
#include <asm/switch_to.h>
#include <asm/uaccess.h>
@@ -227,6 +228,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
pair->value = riscv_cboz_block_size;
break;
+ case RISCV_HWPROBE_KEY_TIME_CSR_FREQ:
+ pair->value = riscv_timebase;
+ break;
+
/*
* For forward compatibility, unknown keys don't fail the whole
* call, but get their element key set to -1 and value set to 0
--
2.20.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH v3] RISC-V: Provide the frequency of time CSR via hwprobe
2024-06-22 2:55 [PATCH v3] RISC-V: Provide the frequency of time CSR via hwprobe Yunhui Cui
@ 2024-06-25 2:08 ` yunhui cui
2024-06-27 8:11 ` Punit Agrawal
2024-06-26 13:01 ` Conor Dooley
1 sibling, 1 reply; 4+ messages in thread
From: yunhui cui @ 2024-06-25 2:08 UTC (permalink / raw)
To: jesse, jrtc27, corbet, paul.walmsley, palmer, aou, cleger, evan,
conor.dooley, cuiyunhui, costa.shul, andy.chiu, samitolvanen,
linux-doc, linux-riscv, linux-kernel, punit.agrawal, Sunil V L
Cc: Palmer Dabbelt, Anup Patel
Add punit and sunil in the loop.
On Sat, Jun 22, 2024 at 10:55 AM Yunhui Cui <cuiyunhui@bytedance.com> wrote:
>
> From: Palmer Dabbelt <palmer@rivosinc.com>
>
> A handful of user-visible behavior is based on the frequency of the
> time CSR.
>
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> Reviewed-by: Evan Green <evan@rivosinc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> Documentation/arch/riscv/hwprobe.rst | 2 ++
> arch/riscv/include/asm/hwprobe.h | 2 +-
> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> arch/riscv/kernel/sys_hwprobe.c | 5 +++++
> 4 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index df5045103e73..ec3c99474ed7 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -233,3 +233,5 @@ The following keys are defined:
>
> * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
> represents the size of the Zicboz block in bytes.
> +
> +* :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`.
> diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
> index 150a9877b0af..ef01c182af2b 100644
> --- a/arch/riscv/include/asm/hwprobe.h
> +++ b/arch/riscv/include/asm/hwprobe.h
> @@ -8,7 +8,7 @@
>
> #include <uapi/asm/hwprobe.h>
>
> -#define RISCV_HWPROBE_MAX_KEY 7
> +#define RISCV_HWPROBE_MAX_KEY 8
>
> static inline bool riscv_hwprobe_key_is_valid(__s64 key)
> {
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 2fb8a8185e7a..5053a9b18710 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -74,6 +74,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
> #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
> #define RISCV_HWPROBE_KEY_MISALIGNED_PERF 7
> +#define RISCV_HWPROBE_KEY_TIME_CSR_FREQ 8
> /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
>
> /* Flags */
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index e4ec9166339f..3d47edc04a3f 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -8,6 +8,7 @@
> #include <asm/cacheflush.h>
> #include <asm/cpufeature.h>
> #include <asm/hwprobe.h>
> +#include <asm/delay.h>
> #include <asm/sbi.h>
> #include <asm/switch_to.h>
> #include <asm/uaccess.h>
> @@ -227,6 +228,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
> pair->value = riscv_cboz_block_size;
> break;
>
> + case RISCV_HWPROBE_KEY_TIME_CSR_FREQ:
> + pair->value = riscv_timebase;
> + break;
> +
> /*
> * For forward compatibility, unknown keys don't fail the whole
> * call, but get their element key set to -1 and value set to 0
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v3] RISC-V: Provide the frequency of time CSR via hwprobe
2024-06-25 2:08 ` yunhui cui
@ 2024-06-27 8:11 ` Punit Agrawal
0 siblings, 0 replies; 4+ messages in thread
From: Punit Agrawal @ 2024-06-27 8:11 UTC (permalink / raw)
To: yunhui cui
Cc: jesse, jrtc27, corbet, paul.walmsley, palmer, aou, cleger, evan,
conor.dooley, costa.shul, andy.chiu, samitolvanen, linux-doc,
linux-riscv, linux-kernel, punit.agrawal, Sunil V L,
Palmer Dabbelt, Anup Patel
yunhui cui <cuiyunhui@bytedance.com> writes:
> Add punit and sunil in the loop.
Thanks for looping us in.
> On Sat, Jun 22, 2024 at 10:55 AM Yunhui Cui <cuiyunhui@bytedance.com> wrote:
>>
>> From: Palmer Dabbelt <palmer@rivosinc.com>
>>
>> A handful of user-visible behavior is based on the frequency of the
>> time CSR.
It will be helpful to add more context to the commit log - especially
for something that is being exposed in a user visible
interface. Something like below -
The RISC-V architecture makes a real time counter CSR (via RDTIME
instruction) available for applications in U-mode but there is no
architected mechanism for an application to discover the frequency
the counter is running at. Some applications (e.g., DPDK) use the
time counter for basic performance analysis as well as fine grained
time-keeping.
Add support to the hwprobe system call to export the timer counter
frequency to code running in U-mode.
With the commit log updated,
Acked-by: Punit Agrawal <punit.agrawal@bytedance.com>
Thanks
>>
>> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
>> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
>> Reviewed-by: Evan Green <evan@rivosinc.com>
>> Reviewed-by: Anup Patel <anup@brainfault.org>
>> ---
>> Documentation/arch/riscv/hwprobe.rst | 2 ++
>> arch/riscv/include/asm/hwprobe.h | 2 +-
>> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
>> arch/riscv/kernel/sys_hwprobe.c | 5 +++++
>> 4 files changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
>> index df5045103e73..ec3c99474ed7 100644
>> --- a/Documentation/arch/riscv/hwprobe.rst
>> +++ b/Documentation/arch/riscv/hwprobe.rst
>> @@ -233,3 +233,5 @@ The following keys are defined:
>>
>> * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
>> represents the size of the Zicboz block in bytes.
>> +
>> +* :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`.
>> diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
>> index 150a9877b0af..ef01c182af2b 100644
>> --- a/arch/riscv/include/asm/hwprobe.h
>> +++ b/arch/riscv/include/asm/hwprobe.h
>> @@ -8,7 +8,7 @@
>>
>> #include <uapi/asm/hwprobe.h>
>>
>> -#define RISCV_HWPROBE_MAX_KEY 7
>> +#define RISCV_HWPROBE_MAX_KEY 8
>>
>> static inline bool riscv_hwprobe_key_is_valid(__s64 key)
>> {
>> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
>> index 2fb8a8185e7a..5053a9b18710 100644
>> --- a/arch/riscv/include/uapi/asm/hwprobe.h
>> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
>> @@ -74,6 +74,7 @@ struct riscv_hwprobe {
>> #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
>> #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
>> #define RISCV_HWPROBE_KEY_MISALIGNED_PERF 7
>> +#define RISCV_HWPROBE_KEY_TIME_CSR_FREQ 8
>> /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
>>
>> /* Flags */
>> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
>> index e4ec9166339f..3d47edc04a3f 100644
>> --- a/arch/riscv/kernel/sys_hwprobe.c
>> +++ b/arch/riscv/kernel/sys_hwprobe.c
>> @@ -8,6 +8,7 @@
>> #include <asm/cacheflush.h>
>> #include <asm/cpufeature.h>
>> #include <asm/hwprobe.h>
>> +#include <asm/delay.h>
>> #include <asm/sbi.h>
>> #include <asm/switch_to.h>
>> #include <asm/uaccess.h>
>> @@ -227,6 +228,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
>> pair->value = riscv_cboz_block_size;
>> break;
>>
>> + case RISCV_HWPROBE_KEY_TIME_CSR_FREQ:
>> + pair->value = riscv_timebase;
>> + break;
>> +
>> /*
>> * For forward compatibility, unknown keys don't fail the whole
>> * call, but get their element key set to -1 and value set to 0
>> --
>> 2.20.1
>>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3] RISC-V: Provide the frequency of time CSR via hwprobe
2024-06-22 2:55 [PATCH v3] RISC-V: Provide the frequency of time CSR via hwprobe Yunhui Cui
2024-06-25 2:08 ` yunhui cui
@ 2024-06-26 13:01 ` Conor Dooley
1 sibling, 0 replies; 4+ messages in thread
From: Conor Dooley @ 2024-06-26 13:01 UTC (permalink / raw)
To: Yunhui Cui
Cc: jesse, jrtc27, corbet, paul.walmsley, palmer, aou, cleger, evan,
conor.dooley, costa.shul, andy.chiu, samitolvanen, linux-doc,
linux-riscv, linux-kernel, Palmer Dabbelt, Anup Patel
[-- Attachment #1: Type: text/plain, Size: 3130 bytes --]
On Sat, Jun 22, 2024 at 10:55:14AM +0800, Yunhui Cui wrote:
> From: Palmer Dabbelt <palmer@rivosinc.com>
>
> A handful of user-visible behavior is based on the frequency of the
> time CSR.
>
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> Reviewed-by: Evan Green <evan@rivosinc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
What changed between this version and the previous one? You need to
include changelogs under the --- for this purpose.
Thanks,
Conor.
> Documentation/arch/riscv/hwprobe.rst | 2 ++
> arch/riscv/include/asm/hwprobe.h | 2 +-
> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> arch/riscv/kernel/sys_hwprobe.c | 5 +++++
> 4 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index df5045103e73..ec3c99474ed7 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -233,3 +233,5 @@ The following keys are defined:
>
> * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
> represents the size of the Zicboz block in bytes.
> +
> +* :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`.
> diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
> index 150a9877b0af..ef01c182af2b 100644
> --- a/arch/riscv/include/asm/hwprobe.h
> +++ b/arch/riscv/include/asm/hwprobe.h
> @@ -8,7 +8,7 @@
>
> #include <uapi/asm/hwprobe.h>
>
> -#define RISCV_HWPROBE_MAX_KEY 7
> +#define RISCV_HWPROBE_MAX_KEY 8
>
> static inline bool riscv_hwprobe_key_is_valid(__s64 key)
> {
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 2fb8a8185e7a..5053a9b18710 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -74,6 +74,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
> #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
> #define RISCV_HWPROBE_KEY_MISALIGNED_PERF 7
> +#define RISCV_HWPROBE_KEY_TIME_CSR_FREQ 8
> /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
>
> /* Flags */
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index e4ec9166339f..3d47edc04a3f 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -8,6 +8,7 @@
> #include <asm/cacheflush.h>
> #include <asm/cpufeature.h>
> #include <asm/hwprobe.h>
> +#include <asm/delay.h>
> #include <asm/sbi.h>
> #include <asm/switch_to.h>
> #include <asm/uaccess.h>
> @@ -227,6 +228,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
> pair->value = riscv_cboz_block_size;
> break;
>
> + case RISCV_HWPROBE_KEY_TIME_CSR_FREQ:
> + pair->value = riscv_timebase;
> + break;
> +
> /*
> * For forward compatibility, unknown keys don't fail the whole
> * call, but get their element key set to -1 and value set to 0
> --
> 2.20.1
>
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2024-06-27 8:11 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2024-06-22 2:55 [PATCH v3] RISC-V: Provide the frequency of time CSR via hwprobe Yunhui Cui
2024-06-25 2:08 ` yunhui cui
2024-06-27 8:11 ` Punit Agrawal
2024-06-26 13:01 ` Conor Dooley
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