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From: Andrew Jones <ajones@ventanamicro.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Albert Ou <aou@eecs.berkeley.edu>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Andrea Parri <parri.andrea@gmail.com>,
	 Nathan Chancellor <nathan@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	 Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>,
	Waiman Long <longman@redhat.com>,
	 Boqun Feng <boqun.feng@gmail.com>, Arnd Bergmann <arnd@arndb.de>,
	 Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>,
	linux-doc@vger.kernel.org,  linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org
Subject: Re: [PATCH v3 01/11] riscv: Implement cmpxchg32/64() using Zacas
Date: Wed, 17 Jul 2024 10:08:19 -0500	[thread overview]
Message-ID: <20240717-8f0afff97de3095badf4fc4e@orel> (raw)
In-Reply-To: <20240717061957.140712-2-alexghiti@rivosinc.com>

On Wed, Jul 17, 2024 at 08:19:47AM GMT, Alexandre Ghiti wrote:
> This adds runtime support for Zacas in cmpxchg operations.
> 
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
>  arch/riscv/Kconfig               | 17 +++++++++++++++++
>  arch/riscv/Makefile              |  3 +++
>  arch/riscv/include/asm/cmpxchg.h | 26 +++++++++++++++++++++++---
>  3 files changed, 43 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 05ccba8ca33a..1caaedec88c7 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -596,6 +596,23 @@ config RISCV_ISA_V_PREEMPTIVE
>  	  preemption. Enabling this config will result in higher memory
>  	  consumption due to the allocation of per-task's kernel Vector context.
>  
> +config TOOLCHAIN_HAS_ZACAS
> +	bool
> +	default y
> +	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zacas)
> +	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zacas)
> +	depends on AS_HAS_OPTION_ARCH
> +
> +config RISCV_ISA_ZACAS
> +	bool "Zacas extension support for atomic CAS"
> +	depends on TOOLCHAIN_HAS_ZACAS
> +	default y
> +	help
> +	  Enable the use of the Zacas ISA-extension to implement kernel atomic
> +	  cmpxchg operations when it is detected at boot.
> +
> +	  If you don't know what to do here, say Y.
> +
>  config TOOLCHAIN_HAS_ZBB
>  	bool
>  	default y
> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> index 06de9d365088..9fd13d7a9cc6 100644
> --- a/arch/riscv/Makefile
> +++ b/arch/riscv/Makefile
> @@ -85,6 +85,9 @@ endif
>  # Check if the toolchain supports Zihintpause extension
>  riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause
>  
> +# Check if the toolchain supports Zacas
> +riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZACAS) := $(riscv-march-y)_zacas
> +
>  # Remove F,D,V from isa string for all. Keep extensions between "fd" and "v" by
>  # matching non-v and non-multi-letter extensions out with the filter ([^v_]*)
>  KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/')
> diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
> index 808b4c78462e..5d38153e2f13 100644
> --- a/arch/riscv/include/asm/cmpxchg.h
> +++ b/arch/riscv/include/asm/cmpxchg.h
> @@ -9,6 +9,7 @@
>  #include <linux/bug.h>
>  
>  #include <asm/fence.h>
> +#include <asm/alternative.h>
>  
>  #define __arch_xchg_masked(sc_sfx, prepend, append, r, p, n)		\
>  ({									\
> @@ -134,21 +135,40 @@
>  	r = (__typeof__(*(p)))((__retx & __mask) >> __s);		\
>  })
>  
> -#define __arch_cmpxchg(lr_sfx, sc_sfx, prepend, append, r, p, co, o, n)	\
> +#define __arch_cmpxchg(lr_sfx, sc_cas_sfx, prepend, append, r, p, co, o, n)	\

I'd either not bother renaming sc_sfx or also rename it in _arch_cmpxchg.

>  ({									\
> +	__label__ no_zacas, end;					\
>  	register unsigned int __rc;					\
>  									\
> +	if (IS_ENABLED(CONFIG_RISCV_ISA_ZACAS)) {			\
> +		asm goto(ALTERNATIVE("j %[no_zacas]", "nop", 0,		\
> +				     RISCV_ISA_EXT_ZACAS, 1)		\
> +			 : : : : no_zacas);				\
> +									\
> +		__asm__ __volatile__ (					\
> +			prepend						\
> +			"	amocas" sc_cas_sfx " %0, %z2, %1\n"	\
> +			append						\
> +			: "+&r" (r), "+A" (*(p))			\
> +			: "rJ" (n)					\
> +			: "memory");					\
> +		goto end;						\
> +	}								\
> +									\
> +no_zacas:								\
>  	__asm__ __volatile__ (						\
>  		prepend							\
>  		"0:	lr" lr_sfx " %0, %2\n"				\
>  		"	bne  %0, %z3, 1f\n"				\
> -		"	sc" sc_sfx " %1, %z4, %2\n"			\
> +		"	sc" sc_cas_sfx " %1, %z4, %2\n"			\
>  		"	bnez %1, 0b\n"					\
>  		append							\
>  		"1:\n"							\
>  		: "=&r" (r), "=&r" (__rc), "+A" (*(p))			\
>  		: "rJ" (co o), "rJ" (n)					\
>  		: "memory");						\
> +									\
> +end:;									\
>  })
>  
>  #define _arch_cmpxchg(ptr, old, new, sc_sfx, prepend, append)		\
> @@ -156,7 +176,7 @@
>  	__typeof__(ptr) __ptr = (ptr);					\
>  	__typeof__(*(__ptr)) __old = (old);				\
>  	__typeof__(*(__ptr)) __new = (new);				\
> -	__typeof__(*(__ptr)) __ret;					\
> +	__typeof__(*(__ptr)) __ret = (old);				\

Is this just to silence some compiler warnings? Can we point out
whatever the reason is in the commit message?

>  									\
>  	switch (sizeof(*__ptr)) {					\
>  	case 1:								\
> -- 
> 2.39.2
>

Thanks,
drew

  reply	other threads:[~2024-07-17 15:08 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-17  6:19 [PATCH v3 00/11] Zacas/Zabha support and qspinlocks Alexandre Ghiti
2024-07-17  6:19 ` [PATCH v3 01/11] riscv: Implement cmpxchg32/64() using Zacas Alexandre Ghiti
2024-07-17 15:08   ` Andrew Jones [this message]
2024-07-17 15:18     ` Alexandre Ghiti
2024-07-19  0:45   ` Samuel Holland
2024-07-19 11:48     ` Alexandre Ghiti
2024-07-19 11:53       ` Alexandre Ghiti
2024-07-17  6:19 ` [PATCH v3 02/11] dt-bindings: riscv: Add Zabha ISA extension description Alexandre Ghiti
2024-07-17  6:42   ` Krzysztof Kozlowski
2024-07-17  9:32   ` Guo Ren
2024-07-17  6:19 ` [PATCH v3 03/11] riscv: Implement cmpxchg8/16() using Zabha Alexandre Ghiti
2024-07-17 15:26   ` Andrew Jones
2024-07-17 15:29     ` Conor Dooley
2024-07-17 15:34       ` Alexandre Ghiti
2024-07-18 12:50     ` Alexandre Ghiti
2024-07-18 16:06       ` Andrew Jones
2024-07-18 16:20         ` Alexandre Ghiti
2024-07-17  6:19 ` [PATCH v3 04/11] riscv: Improve zacas fully-ordered cmpxchg() Alexandre Ghiti
2024-07-17  6:19 ` [PATCH v3 05/11] riscv: Implement arch_cmpxchg128() using Zacas Alexandre Ghiti
2024-07-17 20:34   ` Andrew Jones
2024-07-18  7:48     ` Alexandre Ghiti
2024-07-18  8:33       ` Conor Dooley
2024-07-18  9:35         ` Arnd Bergmann
2024-07-17  6:19 ` [PATCH v3 06/11] riscv: Implement xchg8/16() using Zabha Alexandre Ghiti
2024-07-17  6:19 ` [PATCH v3 07/11] asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock Alexandre Ghiti
2024-07-17  6:19 ` [PATCH v3 08/11] asm-generic: ticket-lock: Add separate ticket-lock.h Alexandre Ghiti
2024-07-17  6:19 ` [PATCH v3 09/11] riscv: Add ISA extension parsing for Ziccrse Alexandre Ghiti
2024-07-19  0:53   ` Samuel Holland
2024-07-19  9:11     ` Alexandre Ghiti
2024-07-17  6:19 ` [PATCH v3 10/11] dt-bindings: riscv: Add Ziccrse ISA extension description Alexandre Ghiti
2024-07-17  6:55   ` Krzysztof Kozlowski
2024-07-17  9:42   ` Guo Ren
2024-07-17  6:19 ` [PATCH v3 11/11] riscv: Add qspinlock support Alexandre Ghiti
2024-07-17  9:30   ` Guo Ren
2024-07-18 13:11     ` Alexandre Ghiti
2024-07-17 16:29   ` Andrea Parri
2024-07-18 13:08     ` Alexandre Ghiti
2024-07-19  1:05   ` Samuel Holland
2024-07-19  9:06     ` Alexandre Ghiti
2024-07-17 16:37 ` [PATCH v3 00/11] Zacas/Zabha support and qspinlocks Andrea Parri

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