From: Jesse Taube <jesse@rivosinc.com>
To: linux-riscv@lists.infradead.org
Cc: "Jonathan Corbet" <corbet@lwn.net>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Clément Léger" <cleger@rivosinc.com>,
"Evan Green" <evan@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Jesse Taube" <jesse@rivosinc.com>,
"Charlie Jenkins" <charlie@rivosinc.com>,
"Xiao Wang" <xiao.w.wang@intel.com>,
"Andy Chiu" <andy.chiu@sifive.com>,
"Eric Biggers" <ebiggers@google.com>,
"Greentime Hu" <greentime.hu@sifive.com>,
"Björn Töpel" <bjorn@rivosinc.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Costa Shulyupin" <costa.shul@redhat.com>,
"Andrew Morton" <akpm@linux-foundation.org>,
"Baoquan He" <bhe@redhat.com>,
"Anup Patel" <apatel@ventanamicro.com>,
"Zong Li" <zong.li@sifive.com>,
"Sami Tolvanen" <samitolvanen@google.com>,
"Ben Dooks" <ben.dooks@codethink.co.uk>,
"Alexandre Ghiti" <alexghiti@rivosinc.com>,
"Gustavo A. R. Silva" <gustavoars@kernel.org>,
"Erick Archer" <erick.archer@gmx.com>,
"Joel Granados" <j.granados@samsung.com>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH v7 0/8] RISC-V: Detect and report speed of unaligned vector accesses
Date: Fri, 26 Jul 2024 12:37:11 -0400 [thread overview]
Message-ID: <20240726163719.1667923-1-jesse@rivosinc.com> (raw)
Adds support for detecting and reporting the speed of unaligned vector
accesses on RISC-V CPUs. Adds vec_misaligned_speed key to the hwprobe
adds Zicclsm to cpufeature and fixes the check for scalar unaligned
emulated all CPUs. The vec_misaligned_speed key keeps the same format
as the scalar unaligned access speed key.
This set does not emulate unaligned vector accesses on CPUs that do not
support them. Only reports if userspace can run them and speed of
unaligned vector accesses if supported.
The Zicclsm is patches are no longer related to this set.
Changes in v6:
Added ("RISC-V: Scalar unaligned access emulated on hotplug CPUs")
Jesse Taube (8):
RISC-V: Add Zicclsm to cpufeature and hwprobe
dt-bindings: riscv: Add Zicclsm ISA extension description.
RISC-V: Check scalar unaligned access on all CPUs
RISC-V: Scalar unaligned access emulated on hotplug CPUs
RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED
RISC-V: Detect unaligned vector accesses supported
RISC-V: Report vector unaligned access speed hwprobe
RISC-V: hwprobe: Document unaligned vector perf key
Documentation/arch/riscv/hwprobe.rst | 21 +++
.../devicetree/bindings/riscv/extensions.yaml | 7 +
arch/riscv/Kconfig | 57 ++++++-
arch/riscv/include/asm/cpufeature.h | 10 +-
arch/riscv/include/asm/entry-common.h | 11 --
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/hwprobe.h | 2 +-
arch/riscv/include/asm/vector.h | 2 +
arch/riscv/include/uapi/asm/hwprobe.h | 6 +
arch/riscv/kernel/Makefile | 3 +-
arch/riscv/kernel/copy-unaligned.h | 5 +
arch/riscv/kernel/cpufeature.c | 1 +
arch/riscv/kernel/fpu.S | 4 +-
arch/riscv/kernel/sys_hwprobe.c | 42 +++++
arch/riscv/kernel/traps_misaligned.c | 131 +++++++++++++--
arch/riscv/kernel/unaligned_access_speed.c | 156 +++++++++++++++++-
arch/riscv/kernel/vec-copy-unaligned.S | 58 +++++++
arch/riscv/kernel/vector.c | 2 +-
18 files changed, 481 insertions(+), 38 deletions(-)
create mode 100644 arch/riscv/kernel/vec-copy-unaligned.S
--
2.45.2
next reply other threads:[~2024-07-26 16:37 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-26 16:37 Jesse Taube [this message]
2024-07-26 16:37 ` [PATCH v7 1/8] RISC-V: Add Zicclsm to cpufeature and hwprobe Jesse Taube
2024-07-26 16:37 ` [PATCH v7 2/8] dt-bindings: riscv: Add Zicclsm ISA extension description Jesse Taube
2024-07-26 16:37 ` [PATCH v7 3/8] RISC-V: Check scalar unaligned access on all CPUs Jesse Taube
2024-07-26 16:37 ` [PATCH v7 4/8] RISC-V: Scalar unaligned access emulated on hotplug CPUs Jesse Taube
2024-07-26 16:37 ` [PATCH v7 5/8] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED Jesse Taube
2024-07-26 16:37 ` [PATCH v7 6/8] RISC-V: Detect unaligned vector accesses supported Jesse Taube
2024-07-26 17:30 ` Evan Green
2024-07-26 16:37 ` [PATCH v7 7/8] RISC-V: Report vector unaligned access speed hwprobe Jesse Taube
2024-07-26 17:30 ` Evan Green
2024-07-26 16:37 ` [PATCH v7 8/8] RISC-V: hwprobe: Document unaligned vector perf key Jesse Taube
2024-07-26 17:30 ` Evan Green
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