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[108.26.179.17]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-200668fc398sm100414505ad.207.2024.08.09.09.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Aug 2024 09:22:54 -0700 (PDT) From: Jesse Taube To: linux-riscv@lists.infradead.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Evan Green , Andrew Jones , Jesse Taube , Charlie Jenkins , Xiao Wang , Andy Chiu , Eric Biggers , Greentime Hu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Heiko Stuebner , Costa Shulyupin , Andrew Morton , Baoquan He , Anup Patel , Zong Li , Sami Tolvanen , Ben Dooks , Alexandre Ghiti , "Gustavo A. R. Silva" , Erick Archer , Joel Granados , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Conor Dooley Subject: [PATCH 2/2] dt-bindings: riscv: Add Zicclsm ISA extension description. Date: Fri, 9 Aug 2024 12:22:40 -0400 Message-ID: <20240809162240.1842373-3-jesse@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240809162240.1842373-1-jesse@rivosinc.com> References: <20240809162240.1842373-1-jesse@rivosinc.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add description for Zicclsm ISA extension. Signed-off-by: Jesse Taube Acked-by: Conor Dooley --- V1 -> V2: - New patch V2 -> V3: - No changes V3 -> V4: - No changes V4 -> V5: - No changes V5 -> V6: - No changes V6 -> V7: - No changes V7 -> V8: - Rebase onto 2d1f51d8a4b0 (palmer/for-next) --- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index a06dbc6b4928..d06ee82abcc1 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -361,6 +361,13 @@ properties: The standard Zicboz extension for cache-block zeroing as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + - const: zicclsm + description: + The standard Zicclsm extension for misaligned support for all regular + load and store instructions (including scalar and vector) but not AMOs + or other specialized forms of memory access. Defined in the + RISC-V RVA Profiles Specification. + - const: zicntr description: The standard Zicntr extension for base counters and timers, as -- 2.45.2