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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95624c1sm474230466b.131.2025.01.13.00.53.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 00:53:59 -0800 (PST) Date: Mon, 13 Jan 2025 09:53:58 +0100 From: Andrew Jones To: Yunhui Cui Cc: alexghiti@rivosinc.com, andybnac@gmail.com, aou@eecs.berkeley.edu, charlie@rivosinc.com, cleger@rivosinc.com, conor.dooley@microchip.com, conor@kernel.org, corbet@lwn.net, evan@rivosinc.com, jesse@rivosinc.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, samuel.holland@sifive.com, shuah@kernel.org Subject: Re: [PATCH v3 1/3] RISC-V: Enable cbo.clean/flush in usermode Message-ID: <20250113-62458ced6e6997eca091f325@orel> References: <20250113083635.73826-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250113083635.73826-1-cuiyunhui@bytedance.com> On Mon, Jan 13, 2025 at 04:36:33PM +0800, Yunhui Cui wrote: > Enabling cbo.clean and cbo.flush in user mode makes it more > convenient to manage the cache state and achieve better performance. > > Reviewed-by: Andrew Jones > Signed-off-by: Yunhui Cui > --- > arch/riscv/kernel/cpufeature.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index c0916ed318c2..60d180b98f52 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -30,6 +30,7 @@ > #define NUM_ALPHA_EXTS ('z' - 'a' + 1) > > static bool any_cpu_has_zicboz; > +static bool any_cpu_has_zicbom; > > unsigned long elf_hwcap __read_mostly; > > @@ -87,6 +88,8 @@ static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data, > pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); > return -EINVAL; > } > + > + any_cpu_has_zicbom = true; > return 0; > } > > @@ -944,6 +947,11 @@ void __init riscv_user_isa_enable(void) > current->thread.envcfg |= ENVCFG_CBZE; > else if (any_cpu_has_zicboz) > pr_warn("Zicboz disabled as it is unavailable on some harts\n"); > + > + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOM)) > + current->thread.envcfg |= ENVCFG_CBCFE; > + else if (any_cpu_has_zicbom) > + pr_warn("Zicbom disabled as it is unavailable on some harts\n"); > } > > #ifdef CONFIG_RISCV_ALTERNATIVE > -- > 2.39.2 > Please use a cover letter with a changelog or at least changelogs under the '---' of each patch. Thanks, drew