From: Andrew Jones <ajones@ventanamicro.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>,
Deepak Gupta <debug@rivosinc.com>
Subject: Re: [PATCH v3 17/17] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG
Date: Thu, 13 Mar 2025 16:23:13 +0100 [thread overview]
Message-ID: <20250313-16176e19c15b63a156cb534c@orel> (raw)
In-Reply-To: <20250310151229.2365992-18-cleger@rivosinc.com>
On Mon, Mar 10, 2025 at 04:12:24PM +0100, Clément Léger wrote:
> SBI_FWFT_MISALIGNED_DELEG needs hedeleg to be modified to delegate
> misaligned load/store exceptions. Save and restore it during CPU
> load/put.
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> Reviewed-by: Deepak Gupta <debug@rivosinc.com>
> ---
> arch/riscv/kvm/vcpu.c | 3 +++
> arch/riscv/kvm/vcpu_sbi_fwft.c | 39 ++++++++++++++++++++++++++++++++++
> 2 files changed, 42 insertions(+)
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 542747e2c7f5..d98e379945c3 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -646,6 +646,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
> {
> void *nsh;
> struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
> + struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
>
> vcpu->cpu = -1;
>
> @@ -671,6 +672,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
> csr->vstval = nacl_csr_read(nsh, CSR_VSTVAL);
> csr->hvip = nacl_csr_read(nsh, CSR_HVIP);
> csr->vsatp = nacl_csr_read(nsh, CSR_VSATP);
> + cfg->hedeleg = nacl_csr_read(nsh, CSR_HEDELEG);
> } else {
> csr->vsstatus = csr_read(CSR_VSSTATUS);
> csr->vsie = csr_read(CSR_VSIE);
> @@ -681,6 +683,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
> csr->vstval = csr_read(CSR_VSTVAL);
> csr->hvip = csr_read(CSR_HVIP);
> csr->vsatp = csr_read(CSR_VSATP);
> + cfg->hedeleg = csr_read(CSR_HEDELEG);
> }
> }
>
> diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c
> index cce1e41d5490..756fda1cf2e7 100644
> --- a/arch/riscv/kvm/vcpu_sbi_fwft.c
> +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c
> @@ -14,6 +14,8 @@
> #include <asm/kvm_vcpu_sbi.h>
> #include <asm/kvm_vcpu_sbi_fwft.h>
>
> +#define MIS_DELEG (BIT_ULL(EXC_LOAD_MISALIGNED) | BIT_ULL(EXC_STORE_MISALIGNED))
> +
> struct kvm_sbi_fwft_feature {
> /**
> * @id: Feature ID
> @@ -64,7 +66,44 @@ static bool kvm_fwft_is_defined_feature(enum sbi_fwft_feature_t feature)
> return false;
> }
>
> +static bool kvm_sbi_fwft_misaligned_delegation_supported(struct kvm_vcpu *vcpu)
> +{
> + if (!misaligned_traps_can_delegate())
> + return false;
> +
> + return true;
Just
return misaligned_traps_can_delegate();
> +}
> +
> +static int kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu,
> + struct kvm_sbi_fwft_config *conf,
> + unsigned long value)
> +{
> + if (value == 1)
> + csr_set(CSR_HEDELEG, MIS_DELEG);
> + else if (value == 0)
> + csr_clear(CSR_HEDELEG, MIS_DELEG);
> + else
> + return SBI_ERR_INVALID_PARAM;
> +
> + return SBI_SUCCESS;
> +}
> +
> +static int kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu,
> + struct kvm_sbi_fwft_config *conf,
> + unsigned long *value)
> +{
> + *value = (csr_read(CSR_HEDELEG) & MIS_DELEG) != 0;
> +
> + return SBI_SUCCESS;
> +}
> +
> static const struct kvm_sbi_fwft_feature features[] = {
> + {
> + .id = SBI_FWFT_MISALIGNED_EXC_DELEG,
> + .supported = kvm_sbi_fwft_misaligned_delegation_supported,
> + .set = kvm_sbi_fwft_set_misaligned_delegation,
> + .get = kvm_sbi_fwft_get_misaligned_delegation,
> + },
> };
>
> static struct kvm_sbi_fwft_config *
> --
> 2.47.2
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
prev parent reply other threads:[~2025-03-13 15:23 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-10 15:12 [PATCH v3 00/17] riscv: add SBI FWFT misaligned exception delegation support Clément Léger
2025-03-10 15:12 ` [PATCH v3 01/17] riscv: add Firmware Feature (FWFT) SBI extensions definitions Clément Léger
2025-03-13 12:24 ` Andrew Jones
2025-03-10 15:12 ` [PATCH v3 02/17] riscv: sbi: add FWFT extension interface Clément Léger
2025-03-13 12:39 ` Andrew Jones
2025-03-14 11:33 ` Clément Léger
2025-03-14 12:02 ` Andrew Jones
2025-03-14 12:23 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 03/17] riscv: sbi: add SBI FWFT extension calls Clément Léger
2025-03-13 12:44 ` Andrew Jones
2025-03-14 11:21 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 04/17] riscv: misaligned: request misaligned exception from SBI Clément Léger
2025-03-13 12:52 ` Andrew Jones
2025-03-10 15:12 ` [PATCH v3 05/17] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing Clément Léger
2025-03-13 12:57 ` Andrew Jones
2025-03-14 11:44 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 06/17] riscv: misaligned: use correct CONFIG_ ifdef for misaligned_access_speed Clément Léger
2025-03-13 13:06 ` Andrew Jones
2025-03-14 11:47 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 07/17] riscv: misaligned: move emulated access uniformity check in a function Clément Léger
2025-03-13 13:07 ` Andrew Jones
2025-03-10 15:12 ` [PATCH v3 08/17] riscv: misaligned: add a function to check misalign trap delegability Clément Léger
2025-03-13 13:19 ` Andrew Jones
2025-03-14 11:49 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 09/17] riscv: misaligned: factorize trap handling Clément Léger
2025-03-10 15:12 ` [PATCH v3 10/17] riscv: misaligned: enable IRQs while handling misaligned accesses Clément Léger
2025-03-10 15:12 ` [PATCH v3 11/17] riscv: misaligned: use get_user() instead of __get_user() Clément Léger
2025-03-10 15:12 ` [PATCH v3 12/17] Documentation/sysctl: add riscv to unaligned-trap supported archs Clément Léger
2025-03-10 15:12 ` [PATCH v3 13/17] selftests: riscv: add misaligned access testing Clément Léger
2025-03-10 15:12 ` [PATCH v3 14/17] RISC-V: KVM: add SBI extension init()/deinit() functions Clément Léger
2025-03-13 14:27 ` Andrew Jones
2025-03-14 13:53 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 15/17] RISC-V: KVM: add SBI extension reset callback Clément Léger
2025-03-13 14:29 ` Andrew Jones
2025-03-10 15:12 ` [PATCH v3 16/17] RISC-V: KVM: add support for FWFT SBI extension Clément Léger
2025-03-13 15:18 ` Andrew Jones
2025-03-10 15:12 ` [PATCH v3 17/17] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Clément Léger
2025-03-13 15:23 ` Andrew Jones [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250313-16176e19c15b63a156cb534c@orel \
--to=ajones@ventanamicro.com \
--cc=anup@brainfault.org \
--cc=atishp@atishpatra.org \
--cc=cleger@rivosinc.com \
--cc=corbet@lwn.net \
--cc=debug@rivosinc.com \
--cc=kvm-riscv@lists.infradead.org \
--cc=kvm@vger.kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-kselftest@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=samuel.holland@sifive.com \
--cc=shuah@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox