From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6496620485B for ; Mon, 17 Mar 2025 17:08:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231310; cv=none; b=jberwXfSIczYEy7lPd03l8rn1289d+22q7aUuOhUqCklHvgQyTW/yfQphu3YL4UGncz3FOwpdMtBgriX7TzSvAMhCJkkRCR2geyiL79XSTTYmMYtnjOib0og4f+LD5+SeMQJ5uyxLdCVYduVxdIHPTgpLrNx9PPP5xpUtXqNcMs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231310; c=relaxed/simple; bh=A4sN/k9udFYHC8rKOJ7GPL1gc/l4wJ5pXjUE1OCS49A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=phOwFt9E+eb6ESL/e/URDQD5gDK9UxpFSgCE2JqZqXaWTNv45dpsIPQGV1lcBwp5NYT5pALZpx3w+T4qXGa4BJIicL+8AMo7VCV2rAn4BTq2fjbV/Oin7aidJ7VpNjxI9EiUAQ3jNfd3lCNYH0iP138TGgZhUgvqiSzWLdwFpo8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=lDAhLQyY; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="lDAhLQyY" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-43cf05f0c3eso17350215e9.0 for ; Mon, 17 Mar 2025 10:08:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231305; x=1742836105; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nBnjzkDoAHCYES1tTH1RlHgMSmamC+5QlhVYnXgdQEI=; b=lDAhLQyYSYSJcmGW+xNXKfAcqyeKyhel8pIznadDrnGv4Rk+7wz31QHjTiGb577KI+ 0ZwdOzQL7V34YMw8sr6RmrsdNOGf1A6T4OhWr7ywBCHHrT2nvP5F/oLOB5S1X8MHOFe/ VF6owPEEmSlZHYJMcaJR0WwSDnHjpiof3i6KjvmzvqFm0muYRjHWk/t8N603i5Kj/EA2 FJ1IS7I670otwVLyRMsGxRSmo/M68hStnqYd37jjHB9bImrdRB26qSI4INyzTC94a/4/ JMEUDByvF7U8lZVnG1cgYsyWTAkO89Arw5CRc2cvhJ0AUZcEMajormoxTKa2tPJTpFip VViQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231305; x=1742836105; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nBnjzkDoAHCYES1tTH1RlHgMSmamC+5QlhVYnXgdQEI=; b=kYkA+nUMqGoAWqxmnBPQ7Hz2OQgF5FeMaigL26rE/4ytBKSfvjx9kQvqnicMCbqJfS 9EFhbz5dEMZw8+uaXjHjDs33AcgEVhZLfT2iCmvExpWHYErKXibaLD1/B3lWyDR1x+3X eF678SQhas9zdeLe2o42hGpXmvA13qDfN+N/JzeUOCGRy5fG8QUDqLAH7hRZ/FsDi57o eAuquC9C+D/SZX0RyrSEB8Vhsb7t8Yifjc+slV44R5rMkms+GDIXELPgjydCl0YxejDn BpSK9hCxn1/gX61u9NbppxHLMDEoNv1xm+coKRFprgWlGyYp5FcygRPaEuNlFH6Um7gO GnDg== X-Forwarded-Encrypted: i=1; AJvYcCUaBfQOUU+ky5W0vi4DHSCCNBijUMtAGtQsC33oCB8Up1uS4eJgv7UkxQFsb2zLMhWW2G8VMdMkLUA=@vger.kernel.org X-Gm-Message-State: AOJu0YxjdVbb5wajX0UnAAzY1JnsXqxOmtd9RMVA2IbaLoAD3m6935ME 9Men4++X/8mrdnj3JT7Yvu0Wh8U+aN2mM+b3z9h83G2ZngJu7gD7ccK4yID1eCY= X-Gm-Gg: ASbGncsxU7I4sUtTPr9uA/MlylO6fD6rQ+awEVdZHcZFMVNBn88S1vnJXU4T7WbpBv/ Gd2gR1mjHMHocCeUjIUsDS6pBEXNbNh0msHZOryEziX2K+ObIN9A3iWVcFVBDn5OGqzKL1t7LRU YTTUveX8gqrDIpp1zI7lRAS3foK0uqL1QHVFS7nImQkPSuQYl930dORlXL80Ww8hvjCL13IHgpr xvyEo+NWzdENOZN5i4ysWDucYQc1M9gC6eR5OIbgRnfGqNXxNnKczsw6SIMIeKPF88Guzm8IopJ g1npZ+D9UQTgCjXkQWuivwWx62PvqZVdmZa/M6RDC/Y5zPAhJYTD3+gH X-Google-Smtp-Source: AGHT+IEqhdp5dcBzbvbBuH3dLSPFcvLdqKUwlLK3z0GBcZnv77CKTJXWVzz2XGRU3Xp4MOn6/tiCWA== X-Received: by 2002:a05:600c:4ed0:b0:43d:ed:acd5 with SMTP id 5b1f17b1804b1-43d2a2eca5bmr70294645e9.10.1742231305531; Mon, 17 Mar 2025 10:08:25 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:24 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 16/18] RISC-V: KVM: add SBI extension reset callback Date: Mon, 17 Mar 2025 18:06:22 +0100 Message-ID: <20250317170625.1142870-17-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, only the STA extension needed a reset function but that's going to be the case for FWFT as well. Add a reset callback that can be implemented by SBI extensions. Signed-off-by: Clément Léger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_host.h | 1 - arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 ++ arch/riscv/kvm/vcpu.c | 2 +- arch/riscv/kvm/vcpu_sbi.c | 24 ++++++++++++++++++++++++ arch/riscv/kvm/vcpu_sbi_sta.c | 3 ++- 5 files changed, 29 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index cc33e35cd628..bb93d2995ea2 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -409,7 +409,6 @@ void __kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); bool kvm_riscv_vcpu_stopped(struct kvm_vcpu *vcpu); -void kvm_riscv_vcpu_sbi_sta_reset(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_record_steal_time(struct kvm_vcpu *vcpu); #endif /* __RISCV_KVM_HOST_H__ */ diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h index bcb90757b149..cb68b3a57c8f 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -57,6 +57,7 @@ struct kvm_vcpu_sbi_extension { */ int (*init)(struct kvm_vcpu *vcpu); void (*deinit)(struct kvm_vcpu *vcpu); + void (*reset)(struct kvm_vcpu *vcpu); }; void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run); @@ -78,6 +79,7 @@ bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx); int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run); void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_sbi_reset(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val); diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 877bcc85c067..542747e2c7f5 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -94,7 +94,7 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) vcpu->arch.hfence_tail = 0; memset(vcpu->arch.hfence_queue, 0, sizeof(vcpu->arch.hfence_queue)); - kvm_riscv_vcpu_sbi_sta_reset(vcpu); + kvm_riscv_vcpu_sbi_reset(vcpu); /* Reset the guest CSRs for hotplug usecase */ if (loaded) diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 3139f171c20f..50be079b5528 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -536,3 +536,27 @@ void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu) ext->deinit(vcpu); } } + +void kvm_riscv_vcpu_sbi_reset(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; + const struct kvm_riscv_sbi_extension_entry *entry; + const struct kvm_vcpu_sbi_extension *ext; + int idx, i; + + for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) { + entry = &sbi_ext[i]; + ext = entry->ext_ptr; + idx = entry->ext_idx; + + if (idx < 0 || idx >= ARRAY_SIZE(scontext->ext_status)) + continue; + + if (scontext->ext_status[idx] != KVM_RISCV_SBI_EXT_STATUS_ENABLED || + !ext->reset) + continue; + + ext->reset(vcpu); + } +} + diff --git a/arch/riscv/kvm/vcpu_sbi_sta.c b/arch/riscv/kvm/vcpu_sbi_sta.c index 5f35427114c1..cc6cb7c8f0e4 100644 --- a/arch/riscv/kvm/vcpu_sbi_sta.c +++ b/arch/riscv/kvm/vcpu_sbi_sta.c @@ -16,7 +16,7 @@ #include #include -void kvm_riscv_vcpu_sbi_sta_reset(struct kvm_vcpu *vcpu) +static void kvm_riscv_vcpu_sbi_sta_reset(struct kvm_vcpu *vcpu) { vcpu->arch.sta.shmem = INVALID_GPA; vcpu->arch.sta.last_steal = 0; @@ -156,6 +156,7 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_sta = { .extid_end = SBI_EXT_STA, .handler = kvm_sbi_ext_sta_handler, .probe = kvm_sbi_ext_sta_probe, + .reset = kvm_riscv_vcpu_sbi_sta_reset, }; int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, -- 2.47.2