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From: Andrew Jones <ajones@ventanamicro.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Anup Patel <anup@brainfault.org>,
	 Atish Patra <atishp@atishpatra.org>,
	Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
	 linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-doc@vger.kernel.org,  kvm@vger.kernel.org,
	kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
	 Samuel Holland <samuel.holland@sifive.com>
Subject: Re: [PATCH v4 02/18] riscv: sbi: add new SBI error mappings
Date: Sat, 22 Mar 2025 13:06:04 +0100	[thread overview]
Message-ID: <20250322-cce038c88db88dd119a49846@orel> (raw)
In-Reply-To: <20250317170625.1142870-3-cleger@rivosinc.com>

On Mon, Mar 17, 2025 at 06:06:08PM +0100, Clément Léger wrote:
> A few new errors have been added with SBI V3.0, maps them as close as
> possible to errno values.
> 
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> ---
>  arch/riscv/include/asm/sbi.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index bb077d0c912f..d11d22717b49 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -536,11 +536,20 @@ static inline int sbi_err_map_linux_errno(int err)
>  	case SBI_SUCCESS:
>  		return 0;
>  	case SBI_ERR_DENIED:
> +	case SBI_ERR_DENIED_LOCKED:
>  		return -EPERM;
>  	case SBI_ERR_INVALID_PARAM:
> +	case SBI_ERR_INVALID_STATE:
> +	case SBI_ERR_BAD_RANGE:
>  		return -EINVAL;
>  	case SBI_ERR_INVALID_ADDRESS:
>  		return -EFAULT;
> +	case SBI_ERR_NO_SHMEM:
> +		return -ENOMEM;
> +	case SBI_ERR_TIMEOUT:
> +		return -ETIME;
> +	case SBI_ERR_IO:
> +		return -EIO;
>  	case SBI_ERR_NOT_SUPPORTED:
>  	case SBI_ERR_FAILURE:
>  	default:
> -- 
> 2.47.2
>

I'm not a huge fan sbi_err_map_linux_errno() since the mappings seem a bit
arbitrary, but if we're going to do it, then these look pretty good to me.
Only other thought I had was E2BIG for bad-range, but nah...

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Thanks,
drew

  reply	other threads:[~2025-03-22 12:06 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-17 17:06 [PATCH v4 00/18] riscv: add SBI FWFT misaligned exception delegation support Clément Léger
2025-03-17 17:06 ` [PATCH v4 01/18] riscv: add Firmware Feature (FWFT) SBI extensions definitions Clément Léger
2025-03-17 17:06 ` [PATCH v4 02/18] riscv: sbi: add new SBI error mappings Clément Léger
2025-03-22 12:06   ` Andrew Jones [this message]
2025-03-24  8:29     ` Clément Léger
2025-03-24  8:38       ` Andrew Jones
2025-03-24  8:40         ` Clément Léger
2025-03-17 17:06 ` [PATCH v4 03/18] riscv: sbi: add FWFT extension interface Clément Léger
2025-03-22 12:11   ` Andrew Jones
2025-03-17 17:06 ` [PATCH v4 04/18] riscv: sbi: add SBI FWFT extension calls Clément Léger
2025-03-22 12:14   ` Andrew Jones
2025-03-24  8:37     ` Clément Léger
2025-03-17 17:06 ` [PATCH v4 05/18] riscv: misaligned: request misaligned exception from SBI Clément Léger
2025-03-17 17:06 ` [PATCH v4 06/18] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing Clément Léger
2025-03-17 17:06 ` [PATCH v4 07/18] riscv: misaligned: use correct CONFIG_ ifdef for misaligned_access_speed Clément Léger
2025-03-17 17:06 ` [PATCH v4 08/18] riscv: misaligned: move emulated access uniformity check in a function Clément Léger
2025-03-17 17:06 ` [PATCH v4 09/18] riscv: misaligned: add a function to check misalign trap delegability Clément Léger
2025-03-17 17:06 ` [PATCH v4 10/18] riscv: misaligned: factorize trap handling Clément Léger
2025-03-17 17:06 ` [PATCH v4 11/18] riscv: misaligned: enable IRQs while handling misaligned accesses Clément Léger
2025-03-17 17:06 ` [PATCH v4 12/18] riscv: misaligned: use get_user() instead of __get_user() Clément Léger
2025-03-17 17:06 ` [PATCH v4 13/18] Documentation/sysctl: add riscv to unaligned-trap supported archs Clément Léger
2025-03-17 17:06 ` [PATCH v4 14/18] selftests: riscv: add misaligned access testing Clément Léger
2025-03-17 17:06 ` [PATCH v4 15/18] RISC-V: KVM: add SBI extension init()/deinit() functions Clément Léger
2025-03-22 12:23   ` Andrew Jones
2025-03-17 17:06 ` [PATCH v4 16/18] RISC-V: KVM: add SBI extension reset callback Clément Léger
2025-03-17 17:06 ` [PATCH v4 17/18] RISC-V: KVM: add support for FWFT SBI extension Clément Léger
2025-03-22 12:30   ` Andrew Jones
2025-03-17 17:06 ` [PATCH v4 18/18] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Clément Léger

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