drivers/gpu/drm/amd/amdgpu/../display/dc/dccg/dcn35/dcn35_dccg.c:1416: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst

[kernel test robot <lkp@intel.com>]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   02ddfb981de88a2c15621115dd7be2431252c568
commit: a3e6079bd93d5c66a43bf6a5f90e5b98465dc7b3 drm/amd/display: Remove PIPE_DTO_SRC_SEL programming from set_dtbclk_dto
date:   5 months ago
config: i386-buildonly-randconfig-002-20250426 (https://download.01.org/0day-ci/archive/20250427/202504270214.c0aGJBHt-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250427/202504270214.c0aGJBHt-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202504270214.c0aGJBHt-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/amd/amdgpu/../display/dc/dccg/dcn35/dcn35_dccg.c:1416: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
                    * PIPEx_DTO_SRC_SEL should not be programmed during DTBCLK update since OTG may still be on, and the


vim +1416 drivers/gpu/drm/amd/amdgpu/../display/dc/dccg/dcn35/dcn35_dccg.c

  1348	
  1349	/* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
  1350	static void dccg35_set_dtbclk_dto(
  1351			struct dccg *dccg,
  1352			const struct dtbclk_dto_params *params)
  1353	{
  1354		struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
  1355		/* DTO Output Rate / Pixel Rate = 1/4 */
  1356		int req_dtbclk_khz = params->pixclk_khz / 4;
  1357	
  1358		if (params->ref_dtbclk_khz && req_dtbclk_khz) {
  1359			uint32_t modulo, phase;
  1360	
  1361			switch (params->otg_inst) {
  1362			case 0:
  1363				REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 1);
  1364				break;
  1365			case 1:
  1366				REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 1);
  1367				break;
  1368			case 2:
  1369				REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 1);
  1370				break;
  1371			case 3:
  1372				REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 1);
  1373				break;
  1374			}
  1375	
  1376			// phase / modulo = dtbclk / dtbclk ref
  1377			modulo = params->ref_dtbclk_khz * 1000;
  1378			phase = req_dtbclk_khz * 1000;
  1379	
  1380			REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
  1381			REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
  1382	
  1383			REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
  1384					DTBCLK_DTO_ENABLE[params->otg_inst], 1);
  1385	
  1386			REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst],
  1387					DTBCLKDTO_ENABLE_STATUS[params->otg_inst], 1,
  1388					1, 100);
  1389	
  1390			/* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */
  1391			dccg35_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);
  1392	
  1393			/* The recommended programming sequence to enable DTBCLK DTO to generate
  1394			 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should
  1395			 * be set only after DTO is enabled.
  1396			 * PIPEx_DTO_SRC_SEL should not be programmed during DTBCLK update since OTG may still be on, and the
  1397			 * programming is handled in program_pix_clk() regardless, so it can be removed from here.
  1398			 */
  1399		} else {
  1400			switch (params->otg_inst) {
  1401			case 0:
  1402				REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 0);
  1403				break;
  1404			case 1:
  1405				REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 0);
  1406				break;
  1407			case 2:
  1408				REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 0);
  1409				break;
  1410			case 3:
  1411				REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 0);
  1412				break;
  1413			}
  1414	
  1415			/**
> 1416			 * PIPEx_DTO_SRC_SEL should not be programmed during DTBCLK update since OTG may still be on, and the
  1417			 * programming is handled in program_pix_clk() regardless, so it can be removed from here.
  1418			 */
  1419			REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
  1420					DTBCLK_DTO_ENABLE[params->otg_inst], 0);
  1421	
  1422			REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
  1423			REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
  1424		}
  1425	}
  1426	

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