* [PATCH v2 01/12] dt-bindings: riscv: Add xsfvqmaccdod and xsfvqmaccqoq ISA extension description
2025-05-16 3:02 [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive Cyan Yang
@ 2025-05-16 3:02 ` Cyan Yang
2025-05-16 3:03 ` [PATCH v2 02/12] riscv: Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions Cyan Yang
` (11 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Cyan Yang @ 2025-05-16 3:02 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, corbet, paul.walmsley, palmer, aou, alex,
samuel.holland
Cc: linux-doc, devicetree, linux-riscv, linux-kernel, Cyan Yang,
Conor Dooley
Add "xsfvqmaccdod" and "xsfvqmaccqoq" ISA extensions which are provided by
SiFive for int8 matrix multiplication instructions support.
Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index bcab59e0cc2e..d36e7c68d69a 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -662,6 +662,19 @@ properties:
Registers in the AX45MP datasheet.
https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+ # SiFive
+ - const: xsfvqmaccdod
+ description:
+ SiFive Int8 Matrix Multiplication Extensions Specification.
+ See more details in
+ https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification
+
+ - const: xsfvqmaccqoq
+ description:
+ SiFive Int8 Matrix Multiplication Extensions Specification.
+ See more details in
+ https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification
+
# T-HEAD
- const: xtheadvector
description:
--
2.39.5 (Apple Git-154)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 02/12] riscv: Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions
2025-05-16 3:02 [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive Cyan Yang
2025-05-16 3:02 ` [PATCH v2 01/12] dt-bindings: riscv: Add xsfvqmaccdod and xsfvqmaccqoq ISA extension description Cyan Yang
@ 2025-05-16 3:03 ` Cyan Yang
2025-05-20 9:26 ` Geert Uytterhoeven
2025-05-16 3:03 ` [PATCH v2 03/12] riscv: hwprobe: Document " Cyan Yang
` (10 subsequent siblings)
12 siblings, 1 reply; 16+ messages in thread
From: Cyan Yang @ 2025-05-16 3:03 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, corbet, paul.walmsley, palmer, aou, alex,
samuel.holland
Cc: linux-doc, devicetree, linux-riscv, linux-kernel, Cyan Yang
Add SiFive vendor extension support to the kernel with the target of
"xsfvqmaccdod" and "xsfvqmaccqoq".
Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
---
arch/riscv/Kconfig.vendor | 13 +++++++++++++
.../include/asm/vendor_extensions/sifive.h | 14 ++++++++++++++
arch/riscv/kernel/vendor_extensions.c | 10 ++++++++++
arch/riscv/kernel/vendor_extensions/Makefile | 1 +
arch/riscv/kernel/vendor_extensions/sifive.c | 19 +++++++++++++++++++
5 files changed, 57 insertions(+)
create mode 100644 arch/riscv/include/asm/vendor_extensions/sifive.h
create mode 100644 arch/riscv/kernel/vendor_extensions/sifive.c
diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor
index b096548fe0ff..e14f26368963 100644
--- a/arch/riscv/Kconfig.vendor
+++ b/arch/riscv/Kconfig.vendor
@@ -16,6 +16,19 @@ config RISCV_ISA_VENDOR_EXT_ANDES
If you don't know what to do here, say Y.
endmenu
+menu "SiFive"
+config RISCV_ISA_VENDOR_EXT_SIFIVE
+ bool "SiFive vendor extension support"
+ select RISCV_ISA_VENDOR_EXT
+ default y
+ help
+ Say N here if you want to disable all SiFive vendor extension
+ support. This will cause any SiFive vendor extensions that are
+ requested by hardware probing to be ignored.
+
+ If you don't know what to do here, say Y.
+endmenu
+
menu "T-Head"
config RISCV_ISA_VENDOR_EXT_THEAD
bool "T-Head vendor extension support"
diff --git a/arch/riscv/include/asm/vendor_extensions/sifive.h b/arch/riscv/include/asm/vendor_extensions/sifive.h
new file mode 100644
index 000000000000..608004250e2e
--- /dev/null
+++ b/arch/riscv/include/asm/vendor_extensions/sifive.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_H
+#define _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_H
+
+#include <asm/vendor_extensions.h>
+
+#include <linux/types.h>
+
+#define RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD 0
+#define RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ 1
+
+extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_sifive;
+
+#endif
diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c
index 9feb7f67a0a3..92d8ff81f42c 100644
--- a/arch/riscv/kernel/vendor_extensions.c
+++ b/arch/riscv/kernel/vendor_extensions.c
@@ -6,6 +6,7 @@
#include <asm/vendorid_list.h>
#include <asm/vendor_extensions.h>
#include <asm/vendor_extensions/andes.h>
+#include <asm/vendor_extensions/sifive.h>
#include <asm/vendor_extensions/thead.h>
#include <linux/array_size.h>
@@ -15,6 +16,9 @@ struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[] = {
#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES
&riscv_isa_vendor_ext_list_andes,
#endif
+#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE
+ &riscv_isa_vendor_ext_list_sifive,
+#endif
#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD
&riscv_isa_vendor_ext_list_thead,
#endif
@@ -45,6 +49,12 @@ bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsig
cpu_bmap = riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap;
break;
#endif
+ #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE
+ case SIFIVE_VENDOR_ID:
+ bmap = &riscv_isa_vendor_ext_list_sifive.all_harts_isa_bitmap;
+ cpu_bmap = riscv_isa_vendor_ext_list_sifive.per_hart_isa_bitmap;
+ break;
+ #endif
#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD
case THEAD_VENDOR_ID:
bmap = &riscv_isa_vendor_ext_list_thead.all_harts_isa_bitmap;
diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile
index 866414c81a9f..d5fdde0e863b 100644
--- a/arch/riscv/kernel/vendor_extensions/Makefile
+++ b/arch/riscv/kernel/vendor_extensions/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o
+obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) += sifive.o
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead.o
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead_hwprobe.o
diff --git a/arch/riscv/kernel/vendor_extensions/sifive.c b/arch/riscv/kernel/vendor_extensions/sifive.c
new file mode 100644
index 000000000000..6042cc3021de
--- /dev/null
+++ b/arch/riscv/kernel/vendor_extensions/sifive.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <asm/cpufeature.h>
+#include <asm/vendor_extensions.h>
+#include <asm/vendor_extensions/sifive.h>
+
+#include <linux/array_size.h>
+#include <linux/types.h>
+
+/* All SiFive vendor extensions supported in Linux */
+static const struct riscv_isa_ext_data riscv_isa_vendor_ext_sifive[] = {
+ __RISCV_ISA_EXT_DATA(xsfvqmaccdod, RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD),
+ __RISCV_ISA_EXT_DATA(xsfvqmaccqoq, RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ),
+};
+
+struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_sifive = {
+ .ext_data_count = ARRAY_SIZE(riscv_isa_vendor_ext_sifive),
+ .ext_data = riscv_isa_vendor_ext_sifive,
+};
--
2.39.5 (Apple Git-154)
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 02/12] riscv: Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions
2025-05-16 3:03 ` [PATCH v2 02/12] riscv: Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions Cyan Yang
@ 2025-05-20 9:26 ` Geert Uytterhoeven
2025-05-22 8:20 ` Cyan Yang
0 siblings, 1 reply; 16+ messages in thread
From: Geert Uytterhoeven @ 2025-05-20 9:26 UTC (permalink / raw)
To: Cyan Yang
Cc: robh, krzk+dt, conor+dt, corbet, paul.walmsley, palmer, aou, alex,
samuel.holland, linux-doc, devicetree, linux-riscv, linux-kernel
Hi Cyan,
On Fri, 16 May 2025 at 05:07, Cyan Yang <cyan.yang@sifive.com> wrote:
> Add SiFive vendor extension support to the kernel with the target of
> "xsfvqmaccdod" and "xsfvqmaccqoq".
>
> Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
Thanks for your patch, which is now commit 2d147d77ae6e96c1 ("riscv:
Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions")
in riscv/for-next.
> --- a/arch/riscv/Kconfig.vendor
> +++ b/arch/riscv/Kconfig.vendor
> @@ -16,6 +16,19 @@ config RISCV_ISA_VENDOR_EXT_ANDES
> If you don't know what to do here, say Y.
> endmenu
>
> +menu "SiFive"
> +config RISCV_ISA_VENDOR_EXT_SIFIVE
> + bool "SiFive vendor extension support"
> + select RISCV_ISA_VENDOR_EXT
> + default y
I guess this has no dependency on ARCH_SIFIVE and does not default
to ARCH_SIFIVE because this extension can be present on non-Sifive
SoCs, too?
Probably I should have asked this when the other RISCV_ISA_VENDOR_EXT_*
were introduced, but at least for ANDES I already know the answer.
> + help
> + Say N here if you want to disable all SiFive vendor extension
> + support. This will cause any SiFive vendor extensions that are
> + requested by hardware probing to be ignored.
> +
> + If you don't know what to do here, say Y.
> +endmenu
> +
> menu "T-Head"
> config RISCV_ISA_VENDOR_EXT_THEAD
> bool "T-Head vendor extension support"
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 02/12] riscv: Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions
2025-05-20 9:26 ` Geert Uytterhoeven
@ 2025-05-22 8:20 ` Cyan Yang
0 siblings, 0 replies; 16+ messages in thread
From: Cyan Yang @ 2025-05-22 8:20 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: robh, krzk+dt, conor+dt, corbet, paul.walmsley, palmer, aou, alex,
samuel.holland, linux-doc, devicetree, linux-riscv, linux-kernel
On Tue, May 20, 2025 at 11:26:39AM +0200, Geert Uytterhoeven wrote:
> Hi Cyan,
>
> On Fri, 16 May 2025 at 05:07, Cyan Yang <cyan.yang@sifive.com> wrote:
> > Add SiFive vendor extension support to the kernel with the target of
> > "xsfvqmaccdod" and "xsfvqmaccqoq".
> >
> > Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
>
> Thanks for your patch, which is now commit 2d147d77ae6e96c1 ("riscv:
> Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions")
> in riscv/for-next.
>
> > --- a/arch/riscv/Kconfig.vendor
> > +++ b/arch/riscv/Kconfig.vendor
> > @@ -16,6 +16,19 @@ config RISCV_ISA_VENDOR_EXT_ANDES
> > If you don't know what to do here, say Y.
> > endmenu
> >
> > +menu "SiFive"
> > +config RISCV_ISA_VENDOR_EXT_SIFIVE
> > + bool "SiFive vendor extension support"
> > + select RISCV_ISA_VENDOR_EXT
> > + default y
>
> I guess this has no dependency on ARCH_SIFIVE and does not default
> to ARCH_SIFIVE because this extension can be present on non-Sifive
> SoCs, too?
>
> Probably I should have asked this when the other RISCV_ISA_VENDOR_EXT_*
> were introduced, but at least for ANDES I already know the answer.
>
Yes, you are right.
ARCH_SIFIVE enables support for SiFive SoC platform.
RISCV_ISA_VENDOR_EXT_SIFIVE enables support for SiFive vendor
extensions, which are not limited to the SiFive SoC platform.
> > + help
> > + Say N here if you want to disable all SiFive vendor extension
> > + support. This will cause any SiFive vendor extensions that are
> > + requested by hardware probing to be ignored.
> > +
> > + If you don't know what to do here, say Y.
> > +endmenu
> > +
> > menu "T-Head"
> > config RISCV_ISA_VENDOR_EXT_THEAD
> > bool "T-Head vendor extension support"
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
Regards,
Cyan
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 03/12] riscv: hwprobe: Document SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions
2025-05-16 3:02 [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive Cyan Yang
2025-05-16 3:02 ` [PATCH v2 01/12] dt-bindings: riscv: Add xsfvqmaccdod and xsfvqmaccqoq ISA extension description Cyan Yang
2025-05-16 3:03 ` [PATCH v2 02/12] riscv: Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions Cyan Yang
@ 2025-05-16 3:03 ` Cyan Yang
2025-05-16 3:03 ` [PATCH v2 04/12] riscv: hwprobe: Add SiFive vendor extension support and probe for xsfqmaccdod and xsfqmaccqoq Cyan Yang
` (9 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Cyan Yang @ 2025-05-16 3:03 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, corbet, paul.walmsley, palmer, aou, alex,
samuel.holland
Cc: linux-doc, devicetree, linux-riscv, linux-kernel, Cyan Yang
Document the support for sifive vendor extensions using the key
RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 and two vendor extensions for SiFive
Int8 Matrix Multiplication Instructions using
RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD and
RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ.
Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
---
Documentation/arch/riscv/hwprobe.rst | 14 ++++++++++++++
arch/riscv/include/asm/hwprobe.h | 2 +-
arch/riscv/include/uapi/asm/hwprobe.h | 1 +
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 53607d962653..16085b2ee64e 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -335,3 +335,17 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which
represents the size of the Zicbom block in bytes.
+
+* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0`: A bitmask containing the
+ sifive vendor extensions that are compatible with the
+ :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
+
+ * SIFIVE
+
+ * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor
+ extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
+ Extensions Specification.
+
+ * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor
+ extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
+ Instruction Extensions Specification.
diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
index 1f690fea0e03..1c6977305776 100644
--- a/arch/riscv/include/asm/hwprobe.h
+++ b/arch/riscv/include/asm/hwprobe.h
@@ -8,7 +8,7 @@
#include <uapi/asm/hwprobe.h>
-#define RISCV_HWPROBE_MAX_KEY 12
+#define RISCV_HWPROBE_MAX_KEY 13
static inline bool riscv_hwprobe_key_is_valid(__s64 key)
{
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 3c2fce939673..9c70101f021b 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -104,6 +104,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED 4
#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 11
#define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 12
+#define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 13
/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
/* Flags */
--
2.39.5 (Apple Git-154)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 04/12] riscv: hwprobe: Add SiFive vendor extension support and probe for xsfqmaccdod and xsfqmaccqoq
2025-05-16 3:02 [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive Cyan Yang
` (2 preceding siblings ...)
2025-05-16 3:03 ` [PATCH v2 03/12] riscv: hwprobe: Document " Cyan Yang
@ 2025-05-16 3:03 ` Cyan Yang
2025-05-16 3:03 ` [PATCH v2 05/12] dt-bindings: riscv: Add xsfvfnrclipxfqf ISA extension description Cyan Yang
` (8 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Cyan Yang @ 2025-05-16 3:03 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, corbet, paul.walmsley, palmer, aou, alex,
samuel.holland
Cc: linux-doc, devicetree, linux-riscv, linux-kernel, Cyan Yang
Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0" which allows
userspace to probe for the new vendor extensions from SiFive. Also, add
new hwprobe for SiFive "xsfvqmaccdod" and "xsfvqmaccqoq" vendor
extensions.
Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
---
arch/riscv/include/asm/hwprobe.h | 1 +
.../asm/vendor_extensions/sifive_hwprobe.h | 19 ++++++++++++++++++
arch/riscv/include/uapi/asm/vendor/sifive.h | 4 ++++
arch/riscv/kernel/sys_hwprobe.c | 5 +++++
arch/riscv/kernel/vendor_extensions/Makefile | 1 +
.../kernel/vendor_extensions/sifive_hwprobe.c | 20 +++++++++++++++++++
6 files changed, 50 insertions(+)
create mode 100644 arch/riscv/include/asm/vendor_extensions/sifive_hwprobe.h
create mode 100644 arch/riscv/include/uapi/asm/vendor/sifive.h
create mode 100644 arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c
diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
index 1c6977305776..7fe0a379474a 100644
--- a/arch/riscv/include/asm/hwprobe.h
+++ b/arch/riscv/include/asm/hwprobe.h
@@ -22,6 +22,7 @@ static inline bool hwprobe_key_is_bitmask(__s64 key)
case RISCV_HWPROBE_KEY_IMA_EXT_0:
case RISCV_HWPROBE_KEY_CPUPERF_0:
case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
+ case RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0:
return true;
}
diff --git a/arch/riscv/include/asm/vendor_extensions/sifive_hwprobe.h b/arch/riscv/include/asm/vendor_extensions/sifive_hwprobe.h
new file mode 100644
index 000000000000..90a61abd033c
--- /dev/null
+++ b/arch/riscv/include/asm/vendor_extensions/sifive_hwprobe.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_HWPROBE_H
+#define _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_HWPROBE_H
+
+#include <linux/cpumask.h>
+
+#include <uapi/asm/hwprobe.h>
+
+#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE
+void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair, const struct cpumask *cpus);
+#else
+static inline void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair,
+ const struct cpumask *cpus)
+{
+ pair->value = 0;
+}
+#endif
+
+#endif
diff --git a/arch/riscv/include/uapi/asm/vendor/sifive.h b/arch/riscv/include/uapi/asm/vendor/sifive.h
new file mode 100644
index 000000000000..f25d8cf110d1
--- /dev/null
+++ b/arch/riscv/include/uapi/asm/vendor/sifive.h
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+
+#define RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD (1 << 0)
+#define RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ (1 << 1)
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 249aec8594a9..138e74f05de7 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -15,6 +15,7 @@
#include <asm/uaccess.h>
#include <asm/unistd.h>
#include <asm/vector.h>
+#include <asm/vendor_extensions/sifive_hwprobe.h>
#include <asm/vendor_extensions/thead_hwprobe.h>
#include <vdso/vsyscall.h>
@@ -300,6 +301,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
pair->value = riscv_timebase;
break;
+ case RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0:
+ hwprobe_isa_vendor_ext_sifive_0(pair, cpus);
+ break;
+
case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
hwprobe_isa_vendor_ext_thead_0(pair, cpus);
break;
diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile
index d5fdde0e863b..a4eca96d1c8a 100644
--- a/arch/riscv/kernel/vendor_extensions/Makefile
+++ b/arch/riscv/kernel/vendor_extensions/Makefile
@@ -2,5 +2,6 @@
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) += sifive.o
+obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) += sifive_hwprobe.o
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead.o
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead_hwprobe.o
diff --git a/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c
new file mode 100644
index 000000000000..461ce0f305ce
--- /dev/null
+++ b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <asm/vendor_extensions/sifive.h>
+#include <asm/vendor_extensions/sifive_hwprobe.h>
+#include <asm/vendor_extensions/vendor_hwprobe.h>
+
+#include <linux/cpumask.h>
+#include <linux/types.h>
+
+#include <uapi/asm/hwprobe.h>
+#include <uapi/asm/vendor/sifive.h>
+
+void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair, const struct cpumask *cpus)
+{
+ VENDOR_EXTENSION_SUPPORTED(pair, cpus,
+ riscv_isa_vendor_ext_list_sifive.per_hart_isa_bitmap, {
+ VENDOR_EXT_KEY(XSFVQMACCDOD);
+ VENDOR_EXT_KEY(XSFVQMACCQOQ);
+ });
+}
--
2.39.5 (Apple Git-154)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 05/12] dt-bindings: riscv: Add xsfvfnrclipxfqf ISA extension description
2025-05-16 3:02 [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive Cyan Yang
` (3 preceding siblings ...)
2025-05-16 3:03 ` [PATCH v2 04/12] riscv: hwprobe: Add SiFive vendor extension support and probe for xsfqmaccdod and xsfqmaccqoq Cyan Yang
@ 2025-05-16 3:03 ` Cyan Yang
2025-05-16 3:03 ` [PATCH v2 06/12] riscv: Add SiFive xsfvfnrclipxfqf vendor extension Cyan Yang
` (7 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Cyan Yang @ 2025-05-16 3:03 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, corbet, paul.walmsley, palmer, aou, alex,
samuel.holland
Cc: linux-doc, devicetree, linux-riscv, linux-kernel, Cyan Yang,
Conor Dooley
Add "xsfvfnrclipxfqf" ISA extension which is provided by SiFive for
FP32-to-int8 ranged clip instructions support.
Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index d36e7c68d69a..be203df29eb8 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -675,6 +675,12 @@ properties:
See more details in
https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification
+ - const: xsfvfnrclipxfqf
+ description:
+ SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification.
+ See more details in
+ https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions
+
# T-HEAD
- const: xtheadvector
description:
--
2.39.5 (Apple Git-154)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 06/12] riscv: Add SiFive xsfvfnrclipxfqf vendor extension
2025-05-16 3:02 [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive Cyan Yang
` (4 preceding siblings ...)
2025-05-16 3:03 ` [PATCH v2 05/12] dt-bindings: riscv: Add xsfvfnrclipxfqf ISA extension description Cyan Yang
@ 2025-05-16 3:03 ` Cyan Yang
2025-05-16 3:03 ` [PATCH v2 07/12] riscv: hwprobe: Document " Cyan Yang
` (6 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Cyan Yang @ 2025-05-16 3:03 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, corbet, paul.walmsley, palmer, aou, alex,
samuel.holland
Cc: linux-doc, devicetree, linux-riscv, linux-kernel, Cyan Yang
Add SiFive vendor extension "xsfvfnrclipxfqf" support to the kernel.
Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
---
arch/riscv/include/asm/vendor_extensions/sifive.h | 1 +
arch/riscv/kernel/vendor_extensions/sifive.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/include/asm/vendor_extensions/sifive.h b/arch/riscv/include/asm/vendor_extensions/sifive.h
index 608004250e2e..2d05e3e73170 100644
--- a/arch/riscv/include/asm/vendor_extensions/sifive.h
+++ b/arch/riscv/include/asm/vendor_extensions/sifive.h
@@ -8,6 +8,7 @@
#define RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD 0
#define RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ 1
+#define RISCV_ISA_VENDOR_EXT_XSFVFNRCLIPXFQF 2
extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_sifive;
diff --git a/arch/riscv/kernel/vendor_extensions/sifive.c b/arch/riscv/kernel/vendor_extensions/sifive.c
index 6042cc3021de..9376e1ce133a 100644
--- a/arch/riscv/kernel/vendor_extensions/sifive.c
+++ b/arch/riscv/kernel/vendor_extensions/sifive.c
@@ -9,6 +9,7 @@
/* All SiFive vendor extensions supported in Linux */
static const struct riscv_isa_ext_data riscv_isa_vendor_ext_sifive[] = {
+ __RISCV_ISA_EXT_DATA(xsfvfnrclipxfqf, RISCV_ISA_VENDOR_EXT_XSFVFNRCLIPXFQF),
__RISCV_ISA_EXT_DATA(xsfvqmaccdod, RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD),
__RISCV_ISA_EXT_DATA(xsfvqmaccqoq, RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ),
};
--
2.39.5 (Apple Git-154)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 07/12] riscv: hwprobe: Document SiFive xsfvfnrclipxfqf vendor extension
2025-05-16 3:02 [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive Cyan Yang
` (5 preceding siblings ...)
2025-05-16 3:03 ` [PATCH v2 06/12] riscv: Add SiFive xsfvfnrclipxfqf vendor extension Cyan Yang
@ 2025-05-16 3:03 ` Cyan Yang
2025-05-16 3:03 ` [PATCH v2 08/12] riscv: hwprobe: Add " Cyan Yang
` (5 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Cyan Yang @ 2025-05-16 3:03 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, corbet, paul.walmsley, palmer, aou, alex,
samuel.holland
Cc: linux-doc, devicetree, linux-riscv, linux-kernel, Cyan Yang
Document the support for SiFive vendor extensions for
FP32-to-int8 Ranged Clip Instructions using
RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF.
Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
---
Documentation/arch/riscv/hwprobe.rst | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 16085b2ee64e..e15405e12239 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -349,3 +349,7 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor
extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
Instruction Extensions Specification.
+
+ * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf
+ vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged
+ Clip Instructions Extensions Specification.
--
2.39.5 (Apple Git-154)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 08/12] riscv: hwprobe: Add SiFive xsfvfnrclipxfqf vendor extension
2025-05-16 3:02 [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive Cyan Yang
` (6 preceding siblings ...)
2025-05-16 3:03 ` [PATCH v2 07/12] riscv: hwprobe: Document " Cyan Yang
@ 2025-05-16 3:03 ` Cyan Yang
2025-05-16 3:03 ` [PATCH v2 09/12] dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description Cyan Yang
` (4 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Cyan Yang @ 2025-05-16 3:03 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, corbet, paul.walmsley, palmer, aou, alex,
samuel.holland
Cc: linux-doc, devicetree, linux-riscv, linux-kernel, Cyan Yang
Add hwprobe for SiFive "xsfvfnrclipxfqf" vendor extension.
Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
---
arch/riscv/include/uapi/asm/vendor/sifive.h | 1 +
arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/vendor/sifive.h b/arch/riscv/include/uapi/asm/vendor/sifive.h
index f25d8cf110d1..b772d4631284 100644
--- a/arch/riscv/include/uapi/asm/vendor/sifive.h
+++ b/arch/riscv/include/uapi/asm/vendor/sifive.h
@@ -2,3 +2,4 @@
#define RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD (1 << 0)
#define RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ (1 << 1)
+#define RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF (1 << 2)
diff --git a/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c
index 461ce0f305ce..2b9505079a9f 100644
--- a/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c
+++ b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c
@@ -16,5 +16,6 @@ void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair, const struct cp
riscv_isa_vendor_ext_list_sifive.per_hart_isa_bitmap, {
VENDOR_EXT_KEY(XSFVQMACCDOD);
VENDOR_EXT_KEY(XSFVQMACCQOQ);
+ VENDOR_EXT_KEY(XSFVFNRCLIPXFQF);
});
}
--
2.39.5 (Apple Git-154)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 09/12] dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description
2025-05-16 3:02 [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive Cyan Yang
` (7 preceding siblings ...)
2025-05-16 3:03 ` [PATCH v2 08/12] riscv: hwprobe: Add " Cyan Yang
@ 2025-05-16 3:03 ` Cyan Yang
2025-05-16 3:03 ` [PATCH v2 10/12] riscv: Add SiFive xsfvfwmaccqqq vendor extension Cyan Yang
` (3 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Cyan Yang @ 2025-05-16 3:03 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, corbet, paul.walmsley, palmer, aou, alex,
samuel.holland
Cc: linux-doc, devicetree, linux-riscv, linux-kernel, Cyan Yang,
Conor Dooley
Add "xsfvfwmaccqqq" ISA extension which is provided by SiFive for
matrix multiply accumulate instructions support.
Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index be203df29eb8..ede6a58ccf53 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -681,6 +681,12 @@ properties:
See more details in
https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions
+ - const: xsfvfwmaccqqq
+ description:
+ SiFive Matrix Multiply Accumulate Instruction Extensions Specification.
+ See more details in
+ https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction
+
# T-HEAD
- const: xtheadvector
description:
--
2.39.5 (Apple Git-154)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 10/12] riscv: Add SiFive xsfvfwmaccqqq vendor extension
2025-05-16 3:02 [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive Cyan Yang
` (8 preceding siblings ...)
2025-05-16 3:03 ` [PATCH v2 09/12] dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description Cyan Yang
@ 2025-05-16 3:03 ` Cyan Yang
2025-05-16 3:03 ` [PATCH v2 11/12] riscv: hwprobe: Document " Cyan Yang
` (2 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Cyan Yang @ 2025-05-16 3:03 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, corbet, paul.walmsley, palmer, aou, alex,
samuel.holland
Cc: linux-doc, devicetree, linux-riscv, linux-kernel, Cyan Yang
Add SiFive vendor extension "xsfvfwmaccqqq" support to the kernel.
Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
---
arch/riscv/include/asm/vendor_extensions/sifive.h | 1 +
arch/riscv/kernel/vendor_extensions/sifive.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/include/asm/vendor_extensions/sifive.h b/arch/riscv/include/asm/vendor_extensions/sifive.h
index 2d05e3e73170..ac00e500361c 100644
--- a/arch/riscv/include/asm/vendor_extensions/sifive.h
+++ b/arch/riscv/include/asm/vendor_extensions/sifive.h
@@ -9,6 +9,7 @@
#define RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD 0
#define RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ 1
#define RISCV_ISA_VENDOR_EXT_XSFVFNRCLIPXFQF 2
+#define RISCV_ISA_VENDOR_EXT_XSFVFWMACCQQQ 3
extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_sifive;
diff --git a/arch/riscv/kernel/vendor_extensions/sifive.c b/arch/riscv/kernel/vendor_extensions/sifive.c
index 9376e1ce133a..8fcf67e8c07f 100644
--- a/arch/riscv/kernel/vendor_extensions/sifive.c
+++ b/arch/riscv/kernel/vendor_extensions/sifive.c
@@ -10,6 +10,7 @@
/* All SiFive vendor extensions supported in Linux */
static const struct riscv_isa_ext_data riscv_isa_vendor_ext_sifive[] = {
__RISCV_ISA_EXT_DATA(xsfvfnrclipxfqf, RISCV_ISA_VENDOR_EXT_XSFVFNRCLIPXFQF),
+ __RISCV_ISA_EXT_DATA(xsfvfwmaccqqq, RISCV_ISA_VENDOR_EXT_XSFVFWMACCQQQ),
__RISCV_ISA_EXT_DATA(xsfvqmaccdod, RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD),
__RISCV_ISA_EXT_DATA(xsfvqmaccqoq, RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ),
};
--
2.39.5 (Apple Git-154)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 11/12] riscv: hwprobe: Document SiFive xsfvfwmaccqqq vendor extension
2025-05-16 3:02 [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive Cyan Yang
` (9 preceding siblings ...)
2025-05-16 3:03 ` [PATCH v2 10/12] riscv: Add SiFive xsfvfwmaccqqq vendor extension Cyan Yang
@ 2025-05-16 3:03 ` Cyan Yang
2025-05-16 3:03 ` [PATCH v2 12/12] riscv: hwprobe: Add " Cyan Yang
2025-06-10 16:28 ` [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive patchwork-bot+linux-riscv
12 siblings, 0 replies; 16+ messages in thread
From: Cyan Yang @ 2025-05-16 3:03 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, corbet, paul.walmsley, palmer, aou, alex,
samuel.holland
Cc: linux-doc, devicetree, linux-riscv, linux-kernel, Cyan Yang
Document the support for matrix multiply accumulate instruction
from SiFive using RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ.
Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
---
Documentation/arch/riscv/hwprobe.rst | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index e15405e12239..7c11351b1383 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -353,3 +353,7 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf
vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged
Clip Instructions Extensions Specification.
+
+ * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
+ vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
+ Instruction Extensions Specification.
\ No newline at end of file
--
2.39.5 (Apple Git-154)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 12/12] riscv: hwprobe: Add SiFive xsfvfwmaccqqq vendor extension
2025-05-16 3:02 [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive Cyan Yang
` (10 preceding siblings ...)
2025-05-16 3:03 ` [PATCH v2 11/12] riscv: hwprobe: Document " Cyan Yang
@ 2025-05-16 3:03 ` Cyan Yang
2025-06-10 16:28 ` [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive patchwork-bot+linux-riscv
12 siblings, 0 replies; 16+ messages in thread
From: Cyan Yang @ 2025-05-16 3:03 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, corbet, paul.walmsley, palmer, aou, alex,
samuel.holland
Cc: linux-doc, devicetree, linux-riscv, linux-kernel, Cyan Yang
Add hwprobe for SiFive "xsfvfwmaccqqq" vendor extension.
Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
---
arch/riscv/include/uapi/asm/vendor/sifive.h | 1 +
arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/vendor/sifive.h b/arch/riscv/include/uapi/asm/vendor/sifive.h
index b772d4631284..9f3278a4b298 100644
--- a/arch/riscv/include/uapi/asm/vendor/sifive.h
+++ b/arch/riscv/include/uapi/asm/vendor/sifive.h
@@ -3,3 +3,4 @@
#define RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD (1 << 0)
#define RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ (1 << 1)
#define RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF (1 << 2)
+#define RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ (1 << 3)
diff --git a/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c
index 2b9505079a9f..1f77f6309763 100644
--- a/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c
+++ b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c
@@ -17,5 +17,6 @@ void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair, const struct cp
VENDOR_EXT_KEY(XSFVQMACCDOD);
VENDOR_EXT_KEY(XSFVQMACCQOQ);
VENDOR_EXT_KEY(XSFVFNRCLIPXFQF);
+ VENDOR_EXT_KEY(XSFVFWMACCQQQ);
});
}
--
2.39.5 (Apple Git-154)
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive
2025-05-16 3:02 [PATCH v2 00/12] riscv: Add vendor extensions support for SiFive Cyan Yang
` (11 preceding siblings ...)
2025-05-16 3:03 ` [PATCH v2 12/12] riscv: hwprobe: Add " Cyan Yang
@ 2025-06-10 16:28 ` patchwork-bot+linux-riscv
12 siblings, 0 replies; 16+ messages in thread
From: patchwork-bot+linux-riscv @ 2025-06-10 16:28 UTC (permalink / raw)
To: Cyan Yang
Cc: linux-riscv, robh, krzk+dt, conor+dt, corbet, paul.walmsley,
palmer, aou, alex, samuel.holland, linux-doc, devicetree,
linux-kernel
Hello:
This series was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Fri, 16 May 2025 11:02:58 +0800 you wrote:
> This patch set adds four vendor-specific ISA extensions from SiFive:
> "xsfvqmaccdod", "xsfvqmaccqoq", "xsfvfnrclipxfqf", and "xsfvfwmaccqqq".
>
> Additionally, a new hwprobe key, RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0,
> has been added to query which SiFive vendor extensions are supported on
> the current platform.
>
> [...]
Here is the summary with links:
- [v2,01/12] dt-bindings: riscv: Add xsfvqmaccdod and xsfvqmaccqoq ISA extension description
https://git.kernel.org/riscv/c/0f733b5be965
- [v2,02/12] riscv: Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions
(no matching commit)
- [v2,03/12] riscv: hwprobe: Document SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions
https://git.kernel.org/riscv/c/e8fd215ed0eb
- [v2,04/12] riscv: hwprobe: Add SiFive vendor extension support and probe for xsfqmaccdod and xsfqmaccqoq
https://git.kernel.org/riscv/c/1a6274f03534
- [v2,05/12] dt-bindings: riscv: Add xsfvfnrclipxfqf ISA extension description
https://git.kernel.org/riscv/c/a5a15e07cbb9
- [v2,06/12] riscv: Add SiFive xsfvfnrclipxfqf vendor extension
(no matching commit)
- [v2,07/12] riscv: hwprobe: Document SiFive xsfvfnrclipxfqf vendor extension
https://git.kernel.org/riscv/c/659d664f7df8
- [v2,08/12] riscv: hwprobe: Add SiFive xsfvfnrclipxfqf vendor extension
https://git.kernel.org/riscv/c/1d91224394c9
- [v2,09/12] dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description
https://git.kernel.org/riscv/c/d5ca02b25f5d
- [v2,10/12] riscv: Add SiFive xsfvfwmaccqqq vendor extension
(no matching commit)
- [v2,11/12] riscv: hwprobe: Document SiFive xsfvfwmaccqqq vendor extension
https://git.kernel.org/riscv/c/a3ca43dc5271
- [v2,12/12] riscv: hwprobe: Add SiFive xsfvfwmaccqqq vendor extension
https://git.kernel.org/riscv/c/d9669e33c8fa
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