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Shutemov" Cc: Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Jonathan Corbet , Andy Lutomirski , Peter Zijlstra , Ard Biesheuvel , Jan Kiszka , Kieran Bingham , Michael Roth , Rick Edgecombe , Brijesh Singh , Sandipan Das , Juergen Gross , Tom Lendacky , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-efi@vger.kernel.org, linux-mm@kvack.org Subject: Re: [PATCHv3 0/4] x86: Make 5-level paging support unconditional for x86-64 Message-ID: <20250517095947.GAaCheE9tUvgSWMhpa@fat_crate.local> References: <20250516123306.3812286-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20250516123306.3812286-1-kirill.shutemov@linux.intel.com> On Fri, May 16, 2025 at 03:33:02PM +0300, Kirill A. Shutemov wrote: > Both Intel and AMD CPUs support 5-level paging, which is expected to > become more widely adopted in the future. > > Remove CONFIG_X86_5LEVEL. > > In preparation to that remove CONFIG_DYNAMIC_MEMORY_LAYOUT and make > SPARSEMEM_VMEMMAP the only memory model. > > v3: > - Drop few "#if CONFIG_PGTABLE_LEVELS >= 5"; > - Make PARAVIRT_XXL 64-bit explicitly and drop ifdefs > to support PGTABLE_LEVELS < 5; > - Add Reviewed-by tags from Ard; > v2: > - Fix 32-bit build by wrapping p4d_set_huge() and p4d_clear_huge() in > #if CONFIG_PGTABLE_LEVELS > 4; > - Rebased onto current tip/master; > > Kirill A. Shutemov (4): > x86/64/mm: Always use dynamic memory layout > x86/64/mm: Make SPARSEMEM_VMEMMAP the only memory model > x86/64/mm: Make 5-level paging support unconditional > x86/paravirt: Restrict PARAVIRT_XXL to 64-bit only The whole set passed randbuilds testing here too, and am running boot tests on my pile of stinky hw. If it passes, we could queue it all. Thx. -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette