From: Andrew Jones <ajones@ventanamicro.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Charlie Jenkins <charlie@rivosinc.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>,
Deepak Gupta <debug@rivosinc.com>
Subject: Re: [PATCH v8 09/14] riscv: misaligned: move emulated access uniformity check in a function
Date: Mon, 26 May 2025 10:41:33 +0200 [thread overview]
Message-ID: <20250526-baaca3f03adcac2b6488f040@orel> (raw)
In-Reply-To: <b2afb9c7-a3d2-4bf6-bfaa-d804358ccd88@rivosinc.com>
On Fri, May 23, 2025 at 09:21:51PM +0200, Clément Léger wrote:
>
>
> On 23/05/2025 20:30, Charlie Jenkins wrote:
> > On Fri, May 23, 2025 at 12:19:26PM +0200, Clément Léger wrote:
> >> Split the code that check for the uniformity of misaligned accesses
> >> performance on all cpus from check_unaligned_access_emulated_all_cpus()
> >> to its own function which will be used for delegation check. No
> >> functional changes intended.
> >>
> >> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> >> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> >> ---
> >> arch/riscv/kernel/traps_misaligned.c | 20 ++++++++++++++------
> >> 1 file changed, 14 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> >> index f1b2af515592..7ecaa8103fe7 100644
> >> --- a/arch/riscv/kernel/traps_misaligned.c
> >> +++ b/arch/riscv/kernel/traps_misaligned.c
> >> @@ -645,6 +645,18 @@ bool __init check_vector_unaligned_access_emulated_all_cpus(void)
> >> }
> >> #endif
> >>
> >> +static bool all_cpus_unaligned_scalar_access_emulated(void)
> >> +{
> >> + int cpu;
> >> +
> >> + for_each_online_cpu(cpu)
> >> + if (per_cpu(misaligned_access_speed, cpu) !=
> >> + RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED)
> >> + return false;
> >> +
> >> + return true;
> >> +}
> >
> > This ends up wasting time when !CONFIG_RISCV_SCALAR_MISALIGNED since it
> > will always return false in that case. Maybe there is a way to simplify
> > the ifdefs and still have performant code, but I don't think this is a
> > big enough problem to prevent this patch from merging.
>
> Yeah I though of that as well but the amount of call to this function is
> probably well below 10 times so I guess it does not really matters in
> that case to justify yet another ifdef ?
Would it need an ifdef? Or can we just do
if (!IS_ENABLED(CONFIG_RISCV_SCALAR_MISALIGNED))
return false;
at the top of the function?
While the function wouldn't waste much time since it's not called much and
would return false on the first check done in the loop, since it's a
static function, adding the IS_ENABLED() check would likely allow the
compiler to completely remove it and all the branches depending on it.
Thanks,
drew
>
> >
> > Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
> > Tested-by: Charlie Jenkins <charlie@rivosinc.com>
>
> Thanks,
>
> Clément
>
> >
> >> +
> >> #ifdef CONFIG_RISCV_SCALAR_MISALIGNED
> >>
> >> static bool unaligned_ctl __read_mostly;
> >> @@ -683,8 +695,6 @@ static int cpu_online_check_unaligned_access_emulated(unsigned int cpu)
> >>
> >> bool __init check_unaligned_access_emulated_all_cpus(void)
> >> {
> >> - int cpu;
> >> -
> >> /*
> >> * We can only support PR_UNALIGN controls if all CPUs have misaligned
> >> * accesses emulated since tasks requesting such control can run on any
> >> @@ -692,10 +702,8 @@ bool __init check_unaligned_access_emulated_all_cpus(void)
> >> */
> >> on_each_cpu(check_unaligned_access_emulated, NULL, 1);
> >>
> >> - for_each_online_cpu(cpu)
> >> - if (per_cpu(misaligned_access_speed, cpu)
> >> - != RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED)
> >> - return false;
> >> + if (!all_cpus_unaligned_scalar_access_emulated())
> >> + return false;
> >>
> >> unaligned_ctl = true;
> >> return true;
> >> --
> >> 2.49.0
> >>
>
next prev parent reply other threads:[~2025-05-26 8:41 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-23 10:19 [PATCH v8 00/14] riscv: add SBI FWFT misaligned exception delegation support Clément Léger
2025-05-23 10:19 ` [PATCH v8 01/14] riscv: sbi: add Firmware Feature (FWFT) SBI extensions definitions Clément Léger
2025-05-23 10:19 ` [PATCH v8 02/14] riscv: sbi: remove useless parenthesis Clément Léger
2025-05-23 10:19 ` [PATCH v8 03/14] riscv: sbi: add new SBI error mappings Clément Léger
2025-05-23 10:19 ` [PATCH v8 04/14] riscv: sbi: add FWFT extension interface Clément Léger
2025-05-23 10:19 ` [PATCH v8 05/14] riscv: sbi: add SBI FWFT extension calls Clément Léger
2025-05-23 10:19 ` [PATCH v8 06/14] riscv: misaligned: request misaligned exception from SBI Clément Léger
2025-05-23 10:19 ` [PATCH v8 07/14] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing Clément Léger
2025-05-23 18:37 ` Charlie Jenkins
2025-05-23 10:19 ` [PATCH v8 08/14] riscv: misaligned: declare misaligned_access_speed under CONFIG_RISCV_MISALIGNED Clément Léger
2025-05-23 18:36 ` Charlie Jenkins
2025-05-29 12:43 ` Andrew Jones
2025-05-23 10:19 ` [PATCH v8 09/14] riscv: misaligned: move emulated access uniformity check in a function Clément Léger
2025-05-23 18:30 ` Charlie Jenkins
2025-05-23 19:21 ` Clément Léger
2025-05-26 8:41 ` Andrew Jones [this message]
2025-05-26 9:38 ` Clément Léger
2025-05-23 10:19 ` [PATCH v8 10/14] riscv: misaligned: add a function to check misalign trap delegability Clément Léger
2025-05-23 18:39 ` Charlie Jenkins
2025-05-23 10:19 ` [PATCH v8 11/14] RISC-V: KVM: add SBI extension init()/deinit() functions Clément Léger
2025-06-12 13:24 ` Anup Patel
2025-05-23 10:19 ` [PATCH v8 12/14] RISC-V: KVM: add SBI extension reset callback Clément Léger
2025-06-12 13:24 ` Anup Patel
2025-05-23 10:19 ` [PATCH v8 13/14] RISC-V: KVM: add support for FWFT SBI extension Clément Léger
2025-05-23 13:05 ` Radim Krčmář
2025-05-23 15:29 ` Clément Léger
2025-05-23 16:27 ` Radim Krčmář
2025-05-23 18:02 ` Atish Patra
2025-05-23 19:23 ` Clément Léger
2025-05-26 8:58 ` Radim Krčmář
2025-06-12 13:25 ` Anup Patel
2025-05-23 10:19 ` [PATCH v8 14/14] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Clément Léger
2025-05-23 13:08 ` Radim Krčmář
2025-06-12 13:26 ` Anup Patel
2025-06-04 18:02 ` [PATCH v8 00/14] riscv: add SBI FWFT misaligned exception delegation support Palmer Dabbelt
2025-06-04 19:32 ` Charlie Jenkins
2025-06-05 7:12 ` Alexandre Ghiti
2025-06-05 1:30 ` patchwork-bot+linux-riscv
2025-08-10 21:12 ` patchwork-bot+linux-riscv
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250526-baaca3f03adcac2b6488f040@orel \
--to=ajones@ventanamicro.com \
--cc=anup@brainfault.org \
--cc=atishp@atishpatra.org \
--cc=charlie@rivosinc.com \
--cc=cleger@rivosinc.com \
--cc=corbet@lwn.net \
--cc=debug@rivosinc.com \
--cc=kvm-riscv@lists.infradead.org \
--cc=kvm@vger.kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-kselftest@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=samuel.holland@sifive.com \
--cc=shuah@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).