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From: Deepak Gupta <debug@rivosinc.com>
To: "Thomas Gleixner" <tglx@linutronix.de>,
	"Ingo Molnar" <mingo@redhat.com>,
	"Borislav Petkov" <bp@alien8.de>,
	"Dave Hansen" <dave.hansen@linux.intel.com>,
	x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
	"Andrew Morton" <akpm@linux-foundation.org>,
	"Liam R. Howlett" <Liam.Howlett@oracle.com>,
	"Vlastimil Babka" <vbabka@suse.cz>,
	"Lorenzo Stoakes" <lorenzo.stoakes@oracle.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Conor Dooley" <conor@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Arnd Bergmann" <arnd@arndb.de>,
	"Christian Brauner" <brauner@kernel.org>,
	"Peter Zijlstra" <peterz@infradead.org>,
	"Oleg Nesterov" <oleg@redhat.com>,
	"Eric Biederman" <ebiederm@xmission.com>,
	"Kees Cook" <kees@kernel.org>, "Jonathan Corbet" <corbet@lwn.net>,
	"Shuah Khan" <shuah@kernel.org>, "Jann Horn" <jannh@google.com>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Miguel Ojeda" <ojeda@kernel.org>,
	"Alex Gaynor" <alex.gaynor@gmail.com>,
	"Boqun Feng" <boqun.feng@gmail.com>,
	"Gary Guo" <gary@garyguo.net>,
	"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
	"Andreas Hindborg" <a.hindborg@kernel.org>,
	"Alice Ryhl" <aliceryhl@google.com>,
	"Trevor Gross" <tmgross@umich.edu>,
	"Benno Lossin" <lossin@kernel.org>
Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org,
	 linux-mm@kvack.org, linux-riscv@lists.infradead.org,
	 devicetree@vger.kernel.org, linux-arch@vger.kernel.org,
	 linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
	 alistair.francis@wdc.com, richard.henderson@linaro.org,
	jim.shu@sifive.com,  andybnac@gmail.com, kito.cheng@sifive.com,
	charlie@rivosinc.com,  atishp@rivosinc.com, evan@rivosinc.com,
	cleger@rivosinc.com,  alexghiti@rivosinc.com,
	samitolvanen@google.com, broonie@kernel.org,
	 rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org
Subject: [PATCH v18 16/27] riscv: signal: abstract header saving for setup_sigcontext
Date: Fri, 11 Jul 2025 12:46:21 -0700	[thread overview]
Message-ID: <20250711-v5_user_cfi_series-v18-16-a8ee62f9f38e@rivosinc.com> (raw)
In-Reply-To: <20250711-v5_user_cfi_series-v18-0-a8ee62f9f38e@rivosinc.com>

From: Andy Chiu <andybnac@gmail.com>

The function save_v_state() served two purposes. First, it saved
extension context into the signal stack. Then, it constructed the
extension header if there was no fault. The second part is independent
of the extension itself. As a result, we can pull that part out, so
future extensions may reuse it. This patch adds arch_ext_list and makes
setup_sigcontext() go through all possible extensions' save() callback.
The callback returns a positive value indicating the size of the
successfully saved extension. Then the kernel proceeds to construct the
header for that extension. The kernel skips an extension if it does
not exist, or if the saving fails for some reasons. The error code is
propagated out on the later case.

This patch does not introduce any functional changes.

Signed-off-by: Andy Chiu <andybnac@gmail.com>
---
 arch/riscv/include/asm/vector.h |  3 ++
 arch/riscv/kernel/signal.c      | 62 +++++++++++++++++++++++++++--------------
 2 files changed, 44 insertions(+), 21 deletions(-)

diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index 45c9b426fcc5..f93b849593c3 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -423,6 +423,9 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; }
 #define riscv_v_thread_free(tsk)		do {} while (0)
 #define  riscv_v_setup_ctx_cache()		do {} while (0)
 #define riscv_v_thread_alloc(tsk)		do {} while (0)
+#define get_cpu_vector_context()		do {} while (0)
+#define put_cpu_vector_context()		do {} while (0)
+#define riscv_v_vstate_set_restore(task, regs)	do {} while (0)
 
 #endif /* CONFIG_RISCV_ISA_V */
 
diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c
index 08378fea3a11..a5e3d54fe54b 100644
--- a/arch/riscv/kernel/signal.c
+++ b/arch/riscv/kernel/signal.c
@@ -68,18 +68,19 @@ static long save_fp_state(struct pt_regs *regs,
 #define restore_fp_state(task, regs) (0)
 #endif
 
-#ifdef CONFIG_RISCV_ISA_V
-
-static long save_v_state(struct pt_regs *regs, void __user **sc_vec)
+static long save_v_state(struct pt_regs *regs, void __user *sc_vec)
 {
-	struct __riscv_ctx_hdr __user *hdr;
 	struct __sc_riscv_v_state __user *state;
 	void __user *datap;
 	long err;
 
-	hdr = *sc_vec;
-	/* Place state to the user's signal context space after the hdr */
-	state = (struct __sc_riscv_v_state __user *)(hdr + 1);
+	if (!IS_ENABLED(CONFIG_RISCV_ISA_V) ||
+	    !((has_vector() || has_xtheadvector()) &&
+	    riscv_v_vstate_query(regs)))
+		return 0;
+
+	/* Place state to the user's signal context spac */
+	state = (struct __sc_riscv_v_state __user *)sc_vec;
 	/* Point datap right after the end of __sc_riscv_v_state */
 	datap = state + 1;
 
@@ -97,15 +98,11 @@ static long save_v_state(struct pt_regs *regs, void __user **sc_vec)
 	err |= __put_user((__force void *)datap, &state->v_state.datap);
 	/* Copy the whole vector content to user space datap. */
 	err |= __copy_to_user(datap, current->thread.vstate.datap, riscv_v_vsize);
-	/* Copy magic to the user space after saving  all vector conetext */
-	err |= __put_user(RISCV_V_MAGIC, &hdr->magic);
-	err |= __put_user(riscv_v_sc_size, &hdr->size);
 	if (unlikely(err))
-		return err;
+		return -EFAULT;
 
-	/* Only progress the sv_vec if everything has done successfully  */
-	*sc_vec += riscv_v_sc_size;
-	return 0;
+	/* Only return the size if everything has done successfully  */
+	return riscv_v_sc_size;
 }
 
 /*
@@ -142,10 +139,20 @@ static long __restore_v_state(struct pt_regs *regs, void __user *sc_vec)
 	 */
 	return copy_from_user(current->thread.vstate.datap, datap, riscv_v_vsize);
 }
-#else
-#define save_v_state(task, regs) (0)
-#define __restore_v_state(task, regs) (0)
-#endif
+
+struct arch_ext_priv {
+	__u32 magic;
+	long (*save)(struct pt_regs *regs, void __user *sc_vec);
+};
+
+struct arch_ext_priv arch_ext_list[] = {
+	{
+		.magic = RISCV_V_MAGIC,
+		.save = &save_v_state,
+	},
+};
+
+const size_t nr_arch_exts = ARRAY_SIZE(arch_ext_list);
 
 static long restore_sigcontext(struct pt_regs *regs,
 	struct sigcontext __user *sc)
@@ -270,7 +277,8 @@ static long setup_sigcontext(struct rt_sigframe __user *frame,
 {
 	struct sigcontext __user *sc = &frame->uc.uc_mcontext;
 	struct __riscv_ctx_hdr __user *sc_ext_ptr = &sc->sc_extdesc.hdr;
-	long err;
+	struct arch_ext_priv *arch_ext;
+	long err, i, ext_size;
 
 	/* sc_regs is structured the same as the start of pt_regs */
 	err = __copy_to_user(&sc->sc_regs, regs, sizeof(sc->sc_regs));
@@ -278,8 +286,20 @@ static long setup_sigcontext(struct rt_sigframe __user *frame,
 	if (has_fpu())
 		err |= save_fp_state(regs, &sc->sc_fpregs);
 	/* Save the vector state. */
-	if ((has_vector() || has_xtheadvector()) && riscv_v_vstate_query(regs))
-		err |= save_v_state(regs, (void __user **)&sc_ext_ptr);
+	for (i = 0; i < nr_arch_exts; i++) {
+		arch_ext = &arch_ext_list[i];
+		if (!arch_ext->save)
+			continue;
+
+		ext_size = arch_ext->save(regs, sc_ext_ptr + 1);
+		if (ext_size <= 0) {
+			err |= ext_size;
+		} else {
+			err |= __put_user(arch_ext->magic, &sc_ext_ptr->magic);
+			err |= __put_user(ext_size, &sc_ext_ptr->size);
+			sc_ext_ptr = (void *)sc_ext_ptr + ext_size;
+		}
+	}
 	/* Write zero to fp-reserved space and check it on restore_sigcontext */
 	err |= __put_user(0, &sc->sc_extdesc.reserved);
 	/* And put END __riscv_ctx_hdr at the end. */

-- 
2.43.0


  parent reply	other threads:[~2025-07-11 19:47 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-11 19:46 [PATCH v18 00/27] riscv control-flow integrity for usermode Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 01/27] mm: VM_SHADOW_STACK definition for riscv Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 02/27] dt-bindings: riscv: zicfilp and zicfiss in dt-bindings (extensions.yaml) Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 03/27] riscv: zicfiss / zicfilp enumeration Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 04/27] riscv: zicfiss / zicfilp extension csr and bit definitions Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 05/27] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 06/27] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 07/27] riscv/mm: manufacture shadow stack pte Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 08/27] riscv/mm: teach pte_mkwrite to manufacture shadow stack PTEs Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 09/27] riscv/mm: write protect and shadow stack Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 10/27] riscv/mm: Implement map_shadow_stack() syscall Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 11/27] riscv/shstk: If needed allocate a new shadow stack on clone Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 12/27] riscv: Implements arch agnostic shadow stack prctls Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 13/27] prctl: arch-agnostic prctl for indirect branch tracking Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 14/27] riscv: Implements arch agnostic indirect branch tracking prctls Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 15/27] riscv/traps: Introduce software check exception and uprobe handling Deepak Gupta
2025-07-11 19:46 ` Deepak Gupta [this message]
2025-07-11 19:46 ` [PATCH v18 17/27] riscv/signal: save and restore of shadow stack for signal Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 18/27] riscv/kernel: update __show_regs to print shadow stack register Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 19/27] riscv/ptrace: riscv cfi status and state via ptrace and in core files Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 20/27] riscv/hwprobe: zicfilp / zicfiss enumeration in hwprobe Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 21/27] riscv: kernel command line option to opt out of user cfi Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 22/27] riscv: enable kernel access to shadow stack memory via FWFT sbi call Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 23/27] arch/riscv: compile vdso with landing pad and shadow stack note Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 24/27] riscv: create a config for shadow stack and landing pad instr support Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 25/27] riscv: Documentation for landing pad / indirect branch tracking Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 26/27] riscv: Documentation for shadow stack on riscv Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 27/27] kselftest/riscv: kselftest for user mode cfi Deepak Gupta
2025-07-11 20:25 ` [PATCH v18 00/27] riscv control-flow integrity for usermode Deepak Gupta

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