From: Krzysztof Kozlowski <krzk@kernel.org>
To: "Clément Le Goffic" <clement.legoffic@foss.st.com>
Cc: Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Jonathan Corbet <corbet@lwn.net>,
Gatien Chevallier <gatien.chevallier@foss.st.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Gabriel Fernandez <gabriel.fernandez@foss.st.com>,
Le Goffic <legoffic.clement@gmail.com>,
Julius Werner <jwerner@chromium.org>,
linux-arm-kernel@lists.infradead.org,
linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org
Subject: Re: [PATCH v3 07/19] dt-bindings: memory: factorise LPDDR channel binding into memory channel
Date: Wed, 23 Jul 2025 08:57:11 +0200 [thread overview]
Message-ID: <20250723-zealous-turtle-of-perfection-e67aee@kuoka> (raw)
In-Reply-To: <20250722-ddrperfm-upstream-v3-7-7b7a4f3dc8a0@foss.st.com>
On Tue, Jul 22, 2025 at 04:03:24PM +0200, Clément Le Goffic wrote:
> LPDDR and DDR channels exist and share the same properties, they have a
> compatible, ranks, and an io-width.
Maybe it is true for all types of SDRAM, like RDRAM and eDRAM, but I
don't think all memory types do.
I think this should be renamed to sdram-channel.
>
> Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
> ---
> ...pddr-channel.yaml => jedec,memory-channel.yaml} | 26 +++++++++++-----------
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,memory-channel.yaml
> similarity index 82%
> rename from Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml
> rename to Documentation/devicetree/bindings/memory-controllers/ddr/jedec,memory-channel.yaml
> index 34b5bd153f63..3bf3a63466eb 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,memory-channel.yaml
> @@ -1,16 +1,16 @@
> # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> %YAML 1.2
> ---
> -$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
> +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,memory-channel.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: LPDDR channel with chip/rank topology description
> +title: Memory channel with chip/rank topology description
>
> description:
> - An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
> - CK, etc.) that connect one or more LPDDR chips to a host system. The main
> - purpose of this node is to overall LPDDR topology of the system, including the
> - amount of individual LPDDR chips and the ranks per chip.
> + A memory channel is a completely independent set of pins (DQ, CA, CS,
A memory channel of SDRAM memory like DDR SDRAM or LPDDR SDRAM is ...
> + CK, etc.) that connect one or more memory chips to a host system. The main
> + purpose of this node is to overall memory topology of the system, including the
> + amount of individual memory chips and the ranks per chip.
>
> maintainers:
> - Julius Werner <jwerner@chromium.org>
> @@ -26,14 +26,14 @@ properties:
> io-width:
> description:
> The number of DQ pins in the channel. If this number is different
> - from (a multiple of) the io-width of the LPDDR chip, that means that
> + from (a multiple of) the io-width of the memory chip, that means that
> multiple instances of that type of chip are wired in parallel on this
> channel (with the channel's DQ pins split up between the different
> chips, and the CA, CS, etc. pins of the different chips all shorted
> together). This means that the total physical memory controlled by a
> channel is equal to the sum of the densities of each rank on the
> - connected LPDDR chip, times the io-width of the channel divided by
> - the io-width of the LPDDR chip.
> + connected memory chip, times the io-width of the channel divided by
> + the io-width of the memory chip.
> enum:
> - 8
> - 16
> @@ -51,8 +51,8 @@ patternProperties:
> "^rank@[0-9]+$":
> type: object
> description:
> - Each physical LPDDR chip may have one or more ranks. Ranks are
> - internal but fully independent sub-units of the chip. Each LPDDR bus
> + Each physical memory chip may have one or more ranks. Ranks are
> + internal but fully independent sub-units of the chip. Each memory bus
> transaction on the channel targets exactly one rank, based on the
> state of the CS pins. Different ranks may have different densities and
> timing requirements.
> @@ -107,7 +107,7 @@ additionalProperties: false
>
> examples:
> - |
> - lpddr-channel0 {
> + memory-channel0 {
If doing this, then separate commit based on generic node name
convention. But then we need to come with generic node name first,
sdram-channel?
And also '-0', not '0' suffix.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-07-23 6:57 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-22 14:03 [PATCH v3 00/19] Introduce STM32 DDR PMU for STM32MP platforms Clément Le Goffic
2025-07-22 14:03 ` [PATCH v3 01/19] bus: firewall: move stm32_firewall header file in include folder Clément Le Goffic
2025-07-22 14:03 ` [PATCH v3 02/19] dt-bindings: stm32: stm32mp25: add `access-controller-cell` property Clément Le Goffic
2025-07-22 14:03 ` [PATCH v3 03/19] clk: stm32mp25: add firewall grant_access ops Clément Le Goffic
2025-07-22 14:03 ` [PATCH v3 04/19] arm64: dts: st: set rcc as an access-controller Clément Le Goffic
2025-07-22 14:03 ` [PATCH v3 05/19] dt-bindings: memory: factorise LPDDR props into memory props Clément Le Goffic
2025-07-22 21:57 ` Julius Werner
2025-07-23 7:21 ` Clement LE GOFFIC
2025-07-22 14:03 ` [PATCH v3 06/19] dt-bindings: memory: introduce DDR4 Clément Le Goffic
2025-07-22 21:57 ` Julius Werner
2025-07-23 7:30 ` Clement LE GOFFIC
2025-07-22 14:03 ` [PATCH v3 07/19] dt-bindings: memory: factorise LPDDR channel binding into memory channel Clément Le Goffic
2025-07-22 21:58 ` Julius Werner
2025-07-23 7:54 ` Clement LE GOFFIC
2025-07-23 6:57 ` Krzysztof Kozlowski [this message]
2025-07-23 7:06 ` Krzysztof Kozlowski
2025-07-23 8:14 ` Clement LE GOFFIC
2025-07-23 8:10 ` Clement LE GOFFIC
2025-07-23 8:18 ` Krzysztof Kozlowski
2025-07-23 21:16 ` Julius Werner
2025-07-22 14:03 ` [PATCH v3 08/19] dt-binding: memory: add DDR4 channel compatible Clément Le Goffic
2025-07-22 14:03 ` [PATCH v3 09/19] arm64: dts: st: add LPDDR channel to stm32mp257f-dk board Clément Le Goffic
2025-07-22 14:03 ` [PATCH v3 10/19] arm64: dts: st: add DDR channel to stm32mp257f-ev1 board Clément Le Goffic
2025-07-22 14:03 ` [PATCH v3 11/19] dt-bindings: perf: stm32: introduce DDRPERFM dt-bindings Clément Le Goffic
2025-07-22 17:01 ` Rob Herring (Arm)
2025-07-22 14:03 ` [PATCH v3 12/19] perf: stm32: introduce DDRPERFM driver Clément Le Goffic
2025-07-25 10:56 ` Jonathan Cameron
2025-07-25 10:59 ` Jonathan Cameron
2025-07-28 13:12 ` Clement LE GOFFIC
2025-07-28 13:12 ` Clement LE GOFFIC
2025-07-22 14:03 ` [PATCH v3 13/19] Documentation: perf: stm32: add ddrperfm support Clément Le Goffic
2025-07-22 14:03 ` [PATCH v3 14/19] MAINTAINERS: add myself as STM32 DDR PMU maintainer Clément Le Goffic
2025-07-22 14:03 ` [PATCH v3 15/19] ARM: dts: stm32: add ddrperfm on stm32mp131 Clément Le Goffic
2025-07-22 14:03 ` [PATCH v3 16/19] ARM: dts: stm32: add ddrperfm on stm32mp151 Clément Le Goffic
2025-07-22 14:03 ` [PATCH v3 17/19] arm64: dts: st: add ddrperfm on stm32mp251 Clément Le Goffic
2025-07-22 14:03 ` [PATCH v3 18/19] arm64: dts: st: support ddrperfm on stm32mp257f-dk Clément Le Goffic
2025-07-22 14:03 ` [PATCH v3 19/19] arm64: dts: st: support ddrperfm on stm32mp257f-ev1 Clément Le Goffic
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