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smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LfD/b5JD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LfD/b5JD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7B785C4CEEF; Thu, 31 Jul 2025 13:54:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753970083; bh=eMaB/jC7BQOujSeVyd65hlSZ/jJUt5A5InXdWSnL42Y=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=LfD/b5JDEM4tfHtFXQ7drTEt8aleNybYQzijLgWsq+p+xNnv2CcV45z6g8k5blx1h LJf5RQXMtCD81I18Q730/r1cE/tRooUKRse/MQ/98Qlo+4ZFt5C5W6s1FmE+UiT+fF fGCKKTUwxi15kn0RnwXrfshq0blX42oaFLSpFa3U91GiH3JSQOhvC16wow3IWEPPzg +pTr7wJssZyyxv0p2wNtIHbABvZknQz/dtOcZFP113btCZgTq6Cw9xoAYeYBAp1nma sfJnJs0Bctps/fzgTBSZSILD6YtS6wqLAFG+Uucid+jkpoas5T2SOHxJMNGtmE2Wsc MbABvN8U+VXfA== Date: Thu, 31 Jul 2025 08:54:42 -0500 From: Rob Herring To: =?iso-8859-1?Q?Cl=E9ment?= Le Goffic Cc: Will Deacon , Mark Rutland , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v5 12/20] dt-bindings: perf: stm32: introduce DDRPERFM dt-bindings Message-ID: <20250731135442.GA2139000-robh@kernel.org> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> <20250728-ddrperfm-upstream-v5-12-03f1be8ad396@foss.st.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250728-ddrperfm-upstream-v5-12-03f1be8ad396@foss.st.com> On Mon, Jul 28, 2025 at 05:29:43PM +0200, Clément Le Goffic wrote: > DDRPERFM is the DDR Performance Monitor embedded in STM32MPU SoC. > It allows to monitor DDR events that come from the DDR Controller > such as read or write events. > > Signed-off-by: Clément Le Goffic > --- > .../devicetree/bindings/perf/st,stm32-ddr-pmu.yaml | 94 ++++++++++++++++++++++ > 1 file changed, 94 insertions(+) > > diff --git a/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml b/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml > new file mode 100644 > index 000000000000..1d97861e3d44 > --- /dev/null > +++ b/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml > @@ -0,0 +1,94 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/perf/st,stm32-ddr-pmu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +maintainers: > + - Clément Le Goffic > + > +title: STMicroelectronics STM32 DDR Performance Monitor (DDRPERFM) > + > +properties: > + compatible: > + oneOf: > + - items: > + - const: st,stm32mp131-ddr-pmu > + - items: > + - enum: > + - st,stm32mp151-ddr-pmu > + - const: st,stm32mp131-ddr-pmu > + - items: > + - const: st,stm32mp251-ddr-pmu This and the 1st entry can be a single enum. > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + access-controllers: > + minItems: 1 > + maxItems: 2 > + > + memory-channel: > + description: > + The memory channel this DDRPERFM is attached to. > + $ref: /schemas/types.yaml#/definitions/phandle > + > +required: > + - compatible > + - reg > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: st,stm32mp131-ddr-pmu > + then: > + required: > + - clocks > + - resets > + > + - if: > + properties: > + compatible: > + contains: > + const: st,stm32mp251-ddr-pmu > + then: > + required: > + - access-controllers > + - memory-channel > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + perf@5a007000 { > + compatible = "st,stm32mp151-ddr-pmu", "st,stm32mp131-ddr-pmu"; > + reg = <0x5a007000 0x400>; > + clocks = <&rcc DDRPERFM>; > + resets = <&rcc DDRPERFM_R>; > + }; > + > + - | > + ddr_channel: sdram-channel-0 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "jedec,ddr4-channel"; > + io-width = <16>; > + }; > + > + perf@48041000 { > + compatible = "st,stm32mp251-ddr-pmu"; > + reg = <0x48041000 0x400>; > + access-controllers = <&rcc 104>; > + memory-channel = <&ddr_channel>; > + }; > > -- > 2.43.0 >