From: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, anup@brainfault.org,
pbonzini@redhat.com, shuah@kernel.org, cyan.yang@sifive.com,
cleger@rivosinc.com, charlie@rivosinc.com,
cuiyunhui@bytedance.com, samuel.holland@sifive.com,
namcao@linutronix.de, jesse@rivosinc.com, inochiama@gmail.com,
yongxuan.wang@sifive.com, ajones@ventanamicro.com,
parri.andrea@gmail.com, mikisabate@gmail.com,
yikming2222@gmail.com, thomas.weissschuh@linutronix.de
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, devicetree@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org, pincheng.plct@isrc.iscas.ac.cn
Subject: [PATCH v1 RESEND 1/5] dt-bidings: riscv: add Zilsd and Zclsd extension descriptions
Date: Thu, 21 Aug 2025 22:01:27 +0800 [thread overview]
Message-ID: <20250821140131.225756-2-pincheng.plct@isrc.iscas.ac.cn> (raw)
In-Reply-To: <20250821140131.225756-1-pincheng.plct@isrc.iscas.ac.cn>
Add descriptions for the Zilsd (Load/Store pair instructions) and
Zclsd (Compressed Load/Store pair instructions) ISA extensions
which were ratified in commit f88abf1 ("Integrating load/store
pair for RV32 with the main manual") of the riscv-isa-manual.
Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
---
.../devicetree/bindings/riscv/extensions.yaml | 39 +++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index ede6a58ccf53..d72ffe8f6fa7 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -366,6 +366,20 @@ properties:
guarantee on LR/SC sequences, as ratified in commit b1d806605f87
("Updated to ratified state.") of the riscv profiles specification.
+ - const: zilsd
+ description:
+ The standard Zilsd extension which provides support for aligned
+ register-pair load and store operations in 32-bit instruction
+ encodings, as ratified in commit f88abf1 ("Integrating
+ load/store pair for RV32 with the main manual") of riscv-isa-manual.
+
+ - const: zclsd
+ description:
+ The Zclsd extension implements the compressed (16-bit) version of the
+ Load/Store Pair for RV32. As with Zilsd, this extension was ratified
+ in commit f88abf1 ("Integrating load/store pair for RV32 with the
+ main manual") of riscv-isa-manual.
+
- const: zk
description:
The standard Zk Standard Scalar cryptography extension as ratified
@@ -847,6 +861,16 @@ properties:
anyOf:
- const: v
- const: zve32x
+ # Zclsd depends on Zilsd and Zca
+ - if:
+ contains:
+ anyOf:
+ - const: zclsd
+ then:
+ contains:
+ anyOf:
+ - const: zilsd
+ - const: zca
allOf:
# Zcf extension does not exist on rv64
@@ -864,6 +888,21 @@ allOf:
not:
contains:
const: zcf
+ # Zilsd extension does not exist on rv64
+ - if:
+ properties:
+ riscv,isa-extensions:
+ contains:
+ const: zilsd
+ riscv,isa-base:
+ contains:
+ const: rv64i
+ then:
+ properties:
+ riscv,isa-extensions:
+ not:
+ contains:
+ const: zilsd
additionalProperties: true
...
--
2.39.5
next prev parent reply other threads:[~2025-08-21 14:02 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-21 14:01 [PATCH v1 RESEND 0/5] RISC-V: Add Zilsd/Zclsd support in hwprobe and KVM Pincheng Wang
2025-08-21 14:01 ` Pincheng Wang [this message]
2025-08-22 16:33 ` [PATCH v1 RESEND 1/5] dt-bidings: riscv: add Zilsd and Zclsd extension descriptions Conor Dooley
2025-08-25 15:26 ` Pincheng Wang
2025-08-25 16:23 ` Conor Dooley
2025-08-22 22:34 ` Inochi Amaoto
2025-08-25 16:19 ` Pincheng Wang
2025-08-21 14:01 ` [PATCH v1 RESEND 2/5] riscv: add ISA extension parsing for Zilsd and Zclsd Pincheng Wang
2025-08-21 14:01 ` [PATCH v1 RESEND 3/5] riscv: hwprobe: export Zilsd and Zclsd ISA extensions Pincheng Wang
2025-08-21 14:01 ` [PATCH v1 RESEND 4/5] riscv: KVM: allow Zilsd and Zclsd extensions for Guest/VM Pincheng Wang
2025-08-21 14:01 ` [PATCH v1 RESEND 5/5] KVM: riscv: selftests: add Zilsd and Zclsd extension to get-reg-list test Pincheng Wang
-- strict thread matches above, loose matches on Subject: below --
2025-08-25 14:58 [PATCH v1 RESEND 1/5] dt-bidings: riscv: add Zilsd and Zclsd extension descriptions pincheng.plct
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