[PATCH v1 RESEND 0/5] RISC-V: Add Zilsd/Zclsd support in hwprobe and KVM

[PATCH v1 RESEND 0/5] RISC-V: Add Zilsd/Zclsd support in hwprobe and KVM

[Pincheng Wang]

Hi all,

This is a RESEND of v1 to correct a mistake in the CC list.
There are **no changes in code** compared to the previous v1.

This patch series adds support for the recently ratified Zilsd
(Load/Store pair instructions) and Zclsd (Compressed Load/Store pair
instructions) extensions to the RISC-V Linux kernel. It covers device tree
binding,ISA string parsing, hwprobe exposure, KVM guest handling and selftests.

Zilsd and Zclsd allow more efficient memory access sequences on RV32. My
goal is to enable glibc and other user-space libraries to detect these
extensions via hwprobe and make use of them for optimized
implementations of common routines. To achieve this, the Linux kernel
needs to recognize and expose the availability of these extensions
through the device tree bindings, ISA string parsing and hwprobe
interfaces. KVM support is also required to correctly virtualize these
features for guest environments.

The series is structured as follows:
- Patch 1: Add device tree bindings documentation for Zilsd and Zclsd
- Patch 2: Extend RISC-V ISA extension string parsing to recognize them.
- Patch 3: Export Zilsd and Zclsd via riscv_hwprobe
- Patch 4: Allow KVM guests to use them.
- Patch 5: Add KVM selftests.

This series of patches is a preparatory step toward enabling user-space
optimizations in glibc that leverage Zilsd and Zclsd, by providing the
necessary kernel-side support.

Please review, and let me know if any adjustments are needed.

Thanks,
Pincheng Wang


Pincheng Wang (5):
  dt-bidings: riscv: add Zilsd and Zclsd extension descriptions
  riscv: add ISA extension parsing for Zilsd and Zclsd:
  riscv: hwprobe: export Zilsd and Zclsd ISA extensions
  riscv: KVM: allow Zilsd and Zclsd extensions for Guest/VM
  KVM: riscv: selftests: add Zilsd and Zclsd extension to get-reg-list
    test

 Documentation/arch/riscv/hwprobe.rst          |  8 ++++
 .../devicetree/bindings/riscv/extensions.yaml | 39 +++++++++++++++++++
 arch/riscv/include/asm/hwcap.h                |  2 +
 arch/riscv/include/uapi/asm/hwprobe.h         |  2 +
 arch/riscv/include/uapi/asm/kvm.h             |  2 +
 arch/riscv/kernel/cpufeature.c                | 24 ++++++++++++
 arch/riscv/kernel/sys_hwprobe.c               |  2 +
 arch/riscv/kvm/vcpu_onereg.c                  |  2 +
 .../selftests/kvm/riscv/get-reg-list.c        |  6 +++
 9 files changed, 87 insertions(+)

-- 
2.39.5

[PATCH v1 RESEND 1/5] dt-bidings: riscv: add Zilsd and Zclsd extension descriptions

[Pincheng Wang]

Add descriptions for the Zilsd (Load/Store pair instructions) and
Zclsd (Compressed Load/Store pair instructions) ISA extensions
which were ratified in commit f88abf1 ("Integrating load/store
pair for RV32 with the main manual") of the riscv-isa-manual.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
---
 .../devicetree/bindings/riscv/extensions.yaml | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index ede6a58ccf53..d72ffe8f6fa7 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -366,6 +366,20 @@ properties:
             guarantee on LR/SC sequences, as ratified in commit b1d806605f87
             ("Updated to ratified state.") of the riscv profiles specification.
 
+        - const: zilsd
+          description:
+            The standard Zilsd extension which provides support for aligned
+            register-pair load and store operations in 32-bit instruction
+            encodings, as ratified in commit f88abf1 ("Integrating
+            load/store pair for RV32 with the main manual") of riscv-isa-manual.
+
+        - const: zclsd
+          description:
+            The Zclsd extension implements the compressed (16-bit) version of the
+            Load/Store Pair for RV32. As with Zilsd, this extension was ratified
+            in commit f88abf1 ("Integrating load/store pair for RV32 with the
+            main manual") of riscv-isa-manual.
+
         - const: zk
           description:
             The standard Zk Standard Scalar cryptography extension as ratified
@@ -847,6 +861,16 @@ properties:
             anyOf:
               - const: v
               - const: zve32x
+      # Zclsd depends on Zilsd and Zca
+      - if:
+          contains:
+            anyOf:
+              - const: zclsd
+        then:
+          contains:
+            anyOf:
+              - const: zilsd
+              - const: zca
 
 allOf:
   # Zcf extension does not exist on rv64
@@ -864,6 +888,21 @@ allOf:
           not:
             contains:
               const: zcf
+  # Zilsd extension does not exist on rv64
+  - if:
+      properties:
+        riscv,isa-extensions:
+          contains:
+            const: zilsd
+        riscv,isa-base:
+          contains:
+            const: rv64i
+    then:
+      properties:
+        riscv,isa-extensions:
+          not:
+            contains:
+              const: zilsd
 
 additionalProperties: true
 ...
-- 
2.39.5

Re: [PATCH v1 RESEND 1/5] dt-bidings: riscv: add Zilsd and Zclsd extension descriptions

[Conor Dooley]

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On Thu, Aug 21, 2025 at 10:01:27PM +0800, Pincheng Wang wrote:
> Add descriptions for the Zilsd (Load/Store pair instructions) and
> Zclsd (Compressed Load/Store pair instructions) ISA extensions
> which were ratified in commit f88abf1 ("Integrating load/store
> pair for RV32 with the main manual") of the riscv-isa-manual.
> 
> Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
> ---
>  .../devicetree/bindings/riscv/extensions.yaml | 39 +++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index ede6a58ccf53..d72ffe8f6fa7 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -366,6 +366,20 @@ properties:
>              guarantee on LR/SC sequences, as ratified in commit b1d806605f87
>              ("Updated to ratified state.") of the riscv profiles specification.
>  
> +        - const: zilsd
> +          description:
> +            The standard Zilsd extension which provides support for aligned
> +            register-pair load and store operations in 32-bit instruction
> +            encodings, as ratified in commit f88abf1 ("Integrating
> +            load/store pair for RV32 with the main manual") of riscv-isa-manual.
> +
> +        - const: zclsd
> +          description:
> +            The Zclsd extension implements the compressed (16-bit) version of the
> +            Load/Store Pair for RV32. As with Zilsd, this extension was ratified
> +            in commit f88abf1 ("Integrating load/store pair for RV32 with the
> +            main manual") of riscv-isa-manual.
> +
>          - const: zk
>            description:
>              The standard Zk Standard Scalar cryptography extension as ratified
> @@ -847,6 +861,16 @@ properties:
>              anyOf:
>                - const: v
>                - const: zve32x
> +      # Zclsd depends on Zilsd and Zca
> +      - if:
> +          contains:
> +            anyOf:
> +              - const: zclsd
> +        then:
> +          contains:
> +            anyOf:
> +              - const: zilsd
> +              - const: zca
>  
>  allOf:
>    # Zcf extension does not exist on rv64
> @@ -864,6 +888,21 @@ allOf:
>            not:
>              contains:
>                const: zcf
> +  # Zilsd extension does not exist on rv64
> +  - if:
> +      properties:

> +        riscv,isa-extensions:
> +          contains:
> +            const: zilsd

This syntax is odd, it shouldn't be required to have zilsd in here and
in the then. Did you copy this from Zcf or come up with it yourself
because it didn't work otherwise?

> +        riscv,isa-base:
> +          contains:
> +            const: rv64i
> +    then:
> +      properties:
> +        riscv,isa-extensions:
> +          not:
> +            contains:
> +              const: zilsd
>  
>  additionalProperties: true
>  ...
> -- 
> 2.39.5
> 

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Re: [PATCH v1 RESEND 1/5] dt-bidings: riscv: add Zilsd and Zclsd extension descriptions

[Pincheng Wang]

On 2025/8/23 0:33, Conor Dooley wrote:
> On Thu, Aug 21, 2025 at 10:01:27PM +0800, Pincheng Wang wrote:
>> Add descriptions for the Zilsd (Load/Store pair instructions) and
>> Zclsd (Compressed Load/Store pair instructions) ISA extensions
>> which were ratified in commit f88abf1 ("Integrating load/store
>> pair for RV32 with the main manual") of the riscv-isa-manual.
>>
>> Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
>> ---
>>   .../devicetree/bindings/riscv/extensions.yaml | 39 +++++++++++++++++++
>>   1 file changed, 39 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
>> index ede6a58ccf53..d72ffe8f6fa7 100644
>> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
>> @@ -366,6 +366,20 @@ properties:
>>               guarantee on LR/SC sequences, as ratified in commit b1d806605f87
>>               ("Updated to ratified state.") of the riscv profiles specification.
>>   
>> +        - const: zilsd
>> +          description:
>> +            The standard Zilsd extension which provides support for aligned
>> +            register-pair load and store operations in 32-bit instruction
>> +            encodings, as ratified in commit f88abf1 ("Integrating
>> +            load/store pair for RV32 with the main manual") of riscv-isa-manual.
>> +
>> +        - const: zclsd
>> +          description:
>> +            The Zclsd extension implements the compressed (16-bit) version of the
>> +            Load/Store Pair for RV32. As with Zilsd, this extension was ratified
>> +            in commit f88abf1 ("Integrating load/store pair for RV32 with the
>> +            main manual") of riscv-isa-manual.
>> +
>>           - const: zk
>>             description:
>>               The standard Zk Standard Scalar cryptography extension as ratified
>> @@ -847,6 +861,16 @@ properties:
>>               anyOf:
>>                 - const: v
>>                 - const: zve32x
>> +      # Zclsd depends on Zilsd and Zca
>> +      - if:
>> +          contains:
>> +            anyOf:
>> +              - const: zclsd
>> +        then:
>> +          contains:
>> +            anyOf:
>> +              - const: zilsd
>> +              - const: zca
>>   
>>   allOf:
>>     # Zcf extension does not exist on rv64
>> @@ -864,6 +888,21 @@ allOf:
>>             not:
>>               contains:
>>                 const: zcf
>> +  # Zilsd extension does not exist on rv64
>> +  - if:
>> +      properties:
> 
>> +        riscv,isa-extensions:
>> +          contains:
>> +            const: zilsd
> 
> This syntax is odd, it shouldn't be required to have zilsd in here and
> in the then. Did you copy this from Zcf or come up with it yourself
> because it didn't work otherwise?
> 

Yes, I did model this after the existing Zcf constraint in the same 
file. The structure is nearly identical: cheking for presence of the 
extension and rv64i, then forbidding it in the "then" branch.

I've tested confirmed that removing the "contains: const: zilsd" from 
the "if" condition still correctly enforces that zilsd must not appear 
when rv64i is present. The "then" clause with "not: contains" is sufficient.

Given that the validation behavior is equivalent, but the logic is 
cleaner and less redundant without the extra "contains", would you 
recommend updating it to the simpler form:

     - if:
         properties:
           riscv,isa-base:
             contains:
               const: rv64i
       then:
         properties:
           riscv,isa-extensions:
             not:
               contains:
                 const: zilsd

If so, I'll update it in the next revision.

Thanks for the review!

Best regards,
Pincheng Wang

>> +        riscv,isa-base:
>> +          contains:
>> +            const: rv64i
>> +    then:
>> +      properties:
>> +        riscv,isa-extensions:
>> +          not:
>> +            contains:
>> +              const: zilsd
>>   
>>   additionalProperties: true
>>   ...
>> -- 
>> 2.39.5
>>

Re: [PATCH v1 RESEND 1/5] dt-bidings: riscv: add Zilsd and Zclsd extension descriptions

[Conor Dooley]

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On Mon, Aug 25, 2025 at 11:26:13PM +0800, Pincheng Wang wrote:
> On 2025/8/23 0:33, Conor Dooley wrote:
> > On Thu, Aug 21, 2025 at 10:01:27PM +0800, Pincheng Wang wrote:
> > > Add descriptions for the Zilsd (Load/Store pair instructions) and
> > > Zclsd (Compressed Load/Store pair instructions) ISA extensions
> > > which were ratified in commit f88abf1 ("Integrating load/store
> > > pair for RV32 with the main manual") of the riscv-isa-manual.
> > > 
> > > Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
> > > ---
> > >   .../devicetree/bindings/riscv/extensions.yaml | 39 +++++++++++++++++++
> > >   1 file changed, 39 insertions(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > index ede6a58ccf53..d72ffe8f6fa7 100644
> > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > @@ -366,6 +366,20 @@ properties:
> > >               guarantee on LR/SC sequences, as ratified in commit b1d806605f87
> > >               ("Updated to ratified state.") of the riscv profiles specification.
> > > +        - const: zilsd
> > > +          description:
> > > +            The standard Zilsd extension which provides support for aligned
> > > +            register-pair load and store operations in 32-bit instruction
> > > +            encodings, as ratified in commit f88abf1 ("Integrating
> > > +            load/store pair for RV32 with the main manual") of riscv-isa-manual.
> > > +
> > > +        - const: zclsd
> > > +          description:
> > > +            The Zclsd extension implements the compressed (16-bit) version of the
> > > +            Load/Store Pair for RV32. As with Zilsd, this extension was ratified
> > > +            in commit f88abf1 ("Integrating load/store pair for RV32 with the
> > > +            main manual") of riscv-isa-manual.
> > > +
> > >           - const: zk
> > >             description:
> > >               The standard Zk Standard Scalar cryptography extension as ratified
> > > @@ -847,6 +861,16 @@ properties:
> > >               anyOf:
> > >                 - const: v
> > >                 - const: zve32x
> > > +      # Zclsd depends on Zilsd and Zca
> > > +      - if:
> > > +          contains:
> > > +            anyOf:
> > > +              - const: zclsd
> > > +        then:
> > > +          contains:
> > > +            anyOf:
> > > +              - const: zilsd
> > > +              - const: zca
> > >   allOf:
> > >     # Zcf extension does not exist on rv64
> > > @@ -864,6 +888,21 @@ allOf:
> > >             not:
> > >               contains:
> > >                 const: zcf
> > > +  # Zilsd extension does not exist on rv64
> > > +  - if:
> > > +      properties:
> > 
> > > +        riscv,isa-extensions:
> > > +          contains:
> > > +            const: zilsd
> > 
> > This syntax is odd, it shouldn't be required to have zilsd in here and
> > in the then. Did you copy this from Zcf or come up with it yourself
> > because it didn't work otherwise?
> > 
> 
> Yes, I did model this after the existing Zcf constraint in the same file.
> The structure is nearly identical: cheking for presence of the extension and
> rv64i, then forbidding it in the "then" branch.
> 
> I've tested confirmed that removing the "contains: const: zilsd" from the
> "if" condition still correctly enforces that zilsd must not appear when
> rv64i is present. The "then" clause with "not: contains" is sufficient.
> 
> Given that the validation behavior is equivalent, but the logic is cleaner
> and less redundant without the extra "contains", would you recommend
> updating it to the simpler form:
> 
>     - if:
>         properties:
>           riscv,isa-base:
>             contains:
>               const: rv64i
>       then:
>         properties:
>           riscv,isa-extensions:
>             not:
>               contains:
>                 const: zilsd
> 
> If so, I'll update it in the next revision.

Yeah, please reduce it to this form.

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Re: [PATCH v1 RESEND 1/5] dt-bidings: riscv: add Zilsd and Zclsd extension descriptions

[Inochi Amaoto]

On Thu, Aug 21, 2025 at 10:01:27PM +0800, Pincheng Wang wrote:
> Add descriptions for the Zilsd (Load/Store pair instructions) and
> Zclsd (Compressed Load/Store pair instructions) ISA extensions
> which were ratified in commit f88abf1 ("Integrating load/store
> pair for RV32 with the main manual") of the riscv-isa-manual.
> 
> Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
> ---
>  .../devicetree/bindings/riscv/extensions.yaml | 39 +++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index ede6a58ccf53..d72ffe8f6fa7 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -366,6 +366,20 @@ properties:
>              guarantee on LR/SC sequences, as ratified in commit b1d806605f87
>              ("Updated to ratified state.") of the riscv profiles specification.
>  
> +        - const: zilsd
> +          description:
> +            The standard Zilsd extension which provides support for aligned
> +            register-pair load and store operations in 32-bit instruction
> +            encodings, as ratified in commit f88abf1 ("Integrating
> +            load/store pair for RV32 with the main manual") of riscv-isa-manual.
> +
> +        - const: zclsd
> +          description:
> +            The Zclsd extension implements the compressed (16-bit) version of the
> +            Load/Store Pair for RV32. As with Zilsd, this extension was ratified
> +            in commit f88abf1 ("Integrating load/store pair for RV32 with the
> +            main manual") of riscv-isa-manual.
> +
>          - const: zk
>            description:
>              The standard Zk Standard Scalar cryptography extension as ratified
> @@ -847,6 +861,16 @@ properties:
>              anyOf:
>                - const: v
>                - const: zve32x

> +      # Zclsd depends on Zilsd and Zca
> +      - if:
> +          contains:
> +            anyOf:
> +              - const: zclsd
> +        then:
> +          contains:
> +            anyOf:
> +              - const: zilsd
> +              - const: zca
>  

Should be allOf? I see the comment says "Zclsd" requires both "Zilsd"
and "Zca".

Regards,
Inochi

Re: [PATCH v1 RESEND 1/5] dt-bidings: riscv: add Zilsd and Zclsd extension descriptions

[Pincheng Wang]

On 2025/8/23 6:34, Inochi Amaoto wrote:
 > On Thu, Aug 21, 2025 at 10:01:27PM +0800, Pincheng Wang wrote:
 >> Add descriptions for the Zilsd (Load/Store pair instructions) and
 >> Zclsd (Compressed Load/Store pair instructions) ISA extensions
 >> which were ratified in commit f88abf1 ("Integrating load/store
 >> pair for RV32 with the main manual") of the riscv-isa-manual.
 >>
 >> Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
 >> ---
 >>   .../devicetree/bindings/riscv/extensions.yaml | 39 +++++++++++++++++++
 >>   1 file changed, 39 insertions(+)
 >>
 >> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml 
b/Documentation/devicetree/bindings/riscv/extensions.yaml
 >> index ede6a58ccf53..d72ffe8f6fa7 100644
 >> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
 >> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
 >> @@ -366,6 +366,20 @@ properties:
 >>               guarantee on LR/SC sequences, as ratified in commit 
b1d806605f87
 >>               ("Updated to ratified state.") of the riscv profiles 
specification.
 >>
 >> +        - const: zilsd
 >> +          description:
 >> +            The standard Zilsd extension which provides support for 
aligned
 >> +            register-pair load and store operations in 32-bit 
instruction
 >> +            encodings, as ratified in commit f88abf1 ("Integrating
 >> +            load/store pair for RV32 with the main manual") of 
riscv-isa-manual.
 >> +
 >> +        - const: zclsd
 >> +          description:
 >> +            The Zclsd extension implements the compressed (16-bit) 
version of the
 >> +            Load/Store Pair for RV32. As with Zilsd, this extension 
was ratified
 >> +            in commit f88abf1 ("Integrating load/store pair for 
RV32 with the
 >> +            main manual") of riscv-isa-manual.
 >> +
 >>           - const: zk
 >>             description:
 >>               The standard Zk Standard Scalar cryptography extension 
as ratified
 >> @@ -847,6 +861,16 @@ properties:
 >>               anyOf:
 >>                 - const: v
 >>                 - const: zve32x
 >
 >> +      # Zclsd depends on Zilsd and Zca
 >> +      - if:
 >> +          contains:
 >> +            anyOf:
 >> +              - const: zclsd
 >> +        then:
 >> +          contains:
 >> +            anyOf:
 >> +              - const: zilsd
 >> +              - const: zca
 >>
 >
 > Should be allOf? I see the comment says "Zclsd" requires both "Zilsd"
 > and "Zca".
 >
 > Regards,
 > Inochi

You're absolutely right, thank you for catching this. Since Zclsd 
depends on both Zilsd and Zca, the condition should use allOf to 
correctly enforce the conjunction. I'll fix this in next revision.

Best regards,
Pincheng Wang

[PATCH v1 RESEND 2/5] riscv: add ISA extension parsing for Zilsd and Zclsd

[Pincheng Wang]

Add parsing for Zilsd and Zclsd ISA extensions which were ratified in
commit f88abf1 ("Integrating load/store pair for RV32 with the
main manual") of the riscv-isa-manual.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
---
 arch/riscv/include/asm/hwcap.h |  2 ++
 arch/riscv/kernel/cpufeature.c | 24 ++++++++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index affd63e11b0a..7ad43d12c49f 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -106,6 +106,8 @@
 #define RISCV_ISA_EXT_ZAAMO		97
 #define RISCV_ISA_EXT_ZALRSC		98
 #define RISCV_ISA_EXT_ZICBOP		99
+#define RISCV_ISA_EXT_ZILSD		100
+#define RISCV_ISA_EXT_ZCLSD     101
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 743d53415572..8e7757db3895 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -242,6 +242,28 @@ static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data,
 	return -EPROBE_DEFER;
 }
 
+static int riscv_ext_zilsd_validate(const struct riscv_isa_ext_data *data,
+		  const unsigned long *isa_bitmap)
+{
+	if (IS_ENABLED(CONFIG_64BIT))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int riscv_ext_zclsd_validate(const struct riscv_isa_ext_data *data,
+				    const unsigned long *isa_bitmap)
+{
+	if (IS_ENABLED(CONFIG_64BIT))
+		return -EINVAL;
+
+	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZILSD) &&
+		__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA))
+		return 0;
+
+	return -EPROBE_DEFER;
+}
+
 static int riscv_vector_f_validate(const struct riscv_isa_ext_data *data,
 				   const unsigned long *isa_bitmap)
 {
@@ -483,6 +505,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA_VALIDATE(zcd, RISCV_ISA_EXT_ZCD, riscv_ext_zcd_validate),
 	__RISCV_ISA_EXT_DATA_VALIDATE(zcf, RISCV_ISA_EXT_ZCF, riscv_ext_zcf_validate),
 	__RISCV_ISA_EXT_DATA_VALIDATE(zcmop, RISCV_ISA_EXT_ZCMOP, riscv_ext_zca_depends),
+	__RISCV_ISA_EXT_DATA_VALIDATE(zclsd, RISCV_ISA_EXT_ZCLSD, riscv_ext_zclsd_validate),
+	__RISCV_ISA_EXT_DATA_VALIDATE(zilsd, RISCV_ISA_EXT_ZILSD, riscv_ext_zilsd_validate),
 	__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
 	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
 	__RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
-- 
2.39.5

[PATCH v1 RESEND 3/5] riscv: hwprobe: export Zilsd and Zclsd ISA extensions

[Pincheng Wang]

Export Zilsd and Zclsd ISA extensions through hwprobe.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
---
 Documentation/arch/riscv/hwprobe.rst  | 8 ++++++++
 arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
 arch/riscv/kernel/sys_hwprobe.c       | 2 ++
 3 files changed, 12 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 2aa9be272d5d..538ab6c08f7b 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -275,6 +275,14 @@ The following keys are defined:
        ratified in commit 49f49c842ff9 ("Update to Rafified state") of
        riscv-zabha.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZILSD`: The Zilsd extension is supported as
+       defined in the RISC-V ISA manual starting from commit f88abf1("Integrating
+       load/store pair for RV32 with the main manual") of the riscv-isa-manual.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZCLSD`: The Zclsd extension is supported as
+       defined in the RISC-V ISA manual starting from commit f88abf1("Integrating
+       load/store pair for RV32 with the main manual") of the riscv-isa-manual.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to
      :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
      mistakenly classified as a bitmask rather than a value.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index aaf6ad970499..e086179bb4fa 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -82,6 +82,8 @@ struct riscv_hwprobe {
 #define		RISCV_HWPROBE_EXT_ZAAMO		(1ULL << 56)
 #define		RISCV_HWPROBE_EXT_ZALRSC	(1ULL << 57)
 #define		RISCV_HWPROBE_EXT_ZABHA		(1ULL << 58)
+#define 	RISCV_HWPROBE_EXT_ZILSD 	(1ULL << 59)
+#define 	RISCV_HWPROBE_EXT_ZCLSD 	(1ULL << 60)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
 #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
 #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 0b170e18a2be..12f4b68ad2ac 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -111,6 +111,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		EXT_KEY(ZCA);
 		EXT_KEY(ZCB);
 		EXT_KEY(ZCMOP);
+		EXT_KEY(ZCLSD);
 		EXT_KEY(ZICBOM);
 		EXT_KEY(ZICBOZ);
 		EXT_KEY(ZICNTR);
@@ -119,6 +120,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		EXT_KEY(ZIHINTPAUSE);
 		EXT_KEY(ZIHPM);
 		EXT_KEY(ZIMOP);
+		EXT_KEY(ZILSD);
 		EXT_KEY(ZKND);
 		EXT_KEY(ZKNE);
 		EXT_KEY(ZKNH);
-- 
2.39.5

[PATCH v1 RESEND 4/5] riscv: KVM: allow Zilsd and Zclsd extensions for Guest/VM

[Pincheng Wang]

Extend the KVM ISA extension ONE_REG interface to allow KVM user space
to detect and enable Zilsd and Zclsd extensions for Guest/VM.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
---
 arch/riscv/include/uapi/asm/kvm.h | 2 ++
 arch/riscv/kvm/vcpu_onereg.c      | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 5f59fd226cc5..beb7ce06dce8 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -174,6 +174,8 @@ enum KVM_RISCV_ISA_EXT_ID {
 	KVM_RISCV_ISA_EXT_ZCD,
 	KVM_RISCV_ISA_EXT_ZCF,
 	KVM_RISCV_ISA_EXT_ZCMOP,
+	KVM_RISCV_ISA_EXT_ZCLSD,
+	KVM_RISCV_ISA_EXT_ZILSD,
 	KVM_RISCV_ISA_EXT_ZAWRS,
 	KVM_RISCV_ISA_EXT_SMNPM,
 	KVM_RISCV_ISA_EXT_SSNPM,
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index 2e1b646f0d61..8219769fc4a1 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -64,6 +64,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
 	KVM_ISA_EXT_ARR(ZCD),
 	KVM_ISA_EXT_ARR(ZCF),
 	KVM_ISA_EXT_ARR(ZCMOP),
+	KVM_ISA_EXT_ARR(ZCLSD),
 	KVM_ISA_EXT_ARR(ZFA),
 	KVM_ISA_EXT_ARR(ZFH),
 	KVM_ISA_EXT_ARR(ZFHMIN),
@@ -78,6 +79,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
 	KVM_ISA_EXT_ARR(ZIHINTPAUSE),
 	KVM_ISA_EXT_ARR(ZIHPM),
 	KVM_ISA_EXT_ARR(ZIMOP),
+	KVM_ISA_EXT_ARR(ZILSD),
 	KVM_ISA_EXT_ARR(ZKND),
 	KVM_ISA_EXT_ARR(ZKNE),
 	KVM_ISA_EXT_ARR(ZKNH),
-- 
2.39.5

[PATCH v1 RESEND 5/5] KVM: riscv: selftests: add Zilsd and Zclsd extension to get-reg-list test

[Pincheng Wang]

The KVM RISC-V allows Zilsd and Zclsd extensions for Guest/VM so add
this extension to get-reg-list test.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
---
 tools/testing/selftests/kvm/riscv/get-reg-list.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index a0b7dabb5040..477bd386265f 100644
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -78,7 +78,9 @@ bool filter_reg(__u64 reg)
 	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB:
 	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD:
 	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF:
+	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCLSD:
 	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP:
+	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZILSD:
 	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA:
 	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH:
 	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:
@@ -530,7 +532,9 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
 		KVM_ISA_EXT_ARR(ZCB),
 		KVM_ISA_EXT_ARR(ZCD),
 		KVM_ISA_EXT_ARR(ZCF),
+		KVM_ISA_EXT_ARR(ZCLSD),
 		KVM_ISA_EXT_ARR(ZCMOP),
+		KVM_ISA_EXT_ARR(ZILSD),
 		KVM_ISA_EXT_ARR(ZFA),
 		KVM_ISA_EXT_ARR(ZFH),
 		KVM_ISA_EXT_ARR(ZFHMIN),
@@ -1199,7 +1203,9 @@ struct vcpu_reg_list *vcpu_configs[] = {
 	&config_zcb,
 	&config_zcd,
 	&config_zcf,
+	&config_zclsd,
 	&config_zcmop,
+	&config_zilsd,
 	&config_zfa,
 	&config_zfh,
 	&config_zfhmin,
-- 
2.39.5