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Date: Thu, 20 Nov 2025 14:18:21 +0000
From: Leo Yan <leo.yan@arm.com>
To: James Clark <james.clark@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jonathan Corbet <corbet@lwn.net>,
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	linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-doc@vger.kernel.org
Subject: Re: [PATCH v5 03/13] coresight: Refactor
 etm4_config_timestamp_event()
Message-ID: <20251120141821.GA724103@e132581.arm.com>
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In-Reply-To: <4090a47c-2208-486b-bd96-47518d7aa90c@linaro.org>

On Thu, Nov 20, 2025 at 01:52:03PM +0000, James Clark wrote:

[...]

> > > +       config->cntr_ctrl[ctridx] = TRCCNTCTLRn_RLDSELF |
> > > +                                   FIELD_PREP(TRCCNTCTLRn_RLDSEL_MASK, ETM_RES_SEL_FALSE) |
> > > +                                   FIELD_PREP(TRCCNTCTLRn_CNTSEL_MASK, ETM_RES_SEL_TRUE);
> > > 
> > 
> > So if we define generic event generators:-
> > 
> > #define ETM4_SEL_RS_PAIR BIT(7)
> > #defiine ETM4_RS_SEL_EVENT_SINGLE(rs_sel_idx) (GENMASK(4:0) & rs_sel_idx)
> > #define ETM4_RS_SEL_EVENT_PAIR(rs_sel_pair_idx) ((GENMASK(3:0) &
> > rs_sel_pair_idx) | ETM4_SEL_RS_PAIR)
> > 
> > these are then reuseable for all registers that need the 8 bit event
> > selectors, beyond just this register.
> > 
> > Thus we now accurately define the fields in the TRCCNTCTLRn
> > 
> > #define TRCCNTCTLRn_RLDEVENT_MASK  GENMASK(15, 8)
> > 
> > and use
> > 
> > FIELD_PREP(TRCCNTCTLRn_RLDEVENT_MASK,
> > ETM4_RS_SEL_EVENT_SINGLE(ETM_RES_SEL_FALSE))
> > 
> > etc.
> > 
> > 
> 
> I'm not sure I agree with that, the Arm ARM has CNTEVENT_TYPE as a regular
> bit in the TRCCNTCTLRn register so it should be set like any other. Hiding
> it as a subfield of "EVENT" when it always exists and always does the same
> thing was maybe seen as a bad decision which is why it was updated?
> 
> Also IMO, beyond using labels instead of raw numbers, the code should just
> show what's programmed into the register. ETM4_RS_SEL_EVENT_SINGLE() would
> be one more macro to jump through to see what's actually happening.

Maybe define a general macro but with extra checking:

  #define TRCCNTCTLRn_RLDEVENT_MASK  GENMASK(15, 8)

  #define ETM4_RS_SEL_EVENT(paired, sel) ({  \
      if (paired)                            \
          assert(!(sel & ~GENMASK(3, 0)));   \
      else                                   \
          assert(!(sel & ~GENMASK(4, 0)));   \
      FIELD_PREP(TRCCNTCTLRn_RLDEVENT_MASK,  \
                 ((paird << 7) | sel));      \
  })

Thanks,
Leo