Re: [PATCH v2 2/2] Documentation/driver-api/cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement

[Jonathan Cameron <jonathan.cameron@huawei.com>]

On Tue, 9 Dec 2025 19:19:56 +0100
Robert Richter <rrichter@amd.com> wrote:

> This adds a convention document for the following patch series:
> 
>  cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement
> 
> Version 7 and later:
> 
>  https://patchwork.kernel.org/project/cxl/cover/20251114213931.30754-1-rrichter@amd.com/

Can we make that a Link: tag as part of the main tag block? Perhaps
better to refer to lore.kernel.org rather than patchwork? 


> 
> Reviewed-by: Gregory Price <gourry@gourry.net>
> Signed-off-by: Robert Richter <rrichter@amd.com>

A few minor things inline around constraining the explanation a little so
as not to imply more general CXL restrictions.

Thanks,

Jonathan


> ---
> v2:
>  * updated sob-chain,
>  * spell fix in patch description (Randy),
>  * made small changes as suggested by Randy,
>  * Removed include:: <isonum.txt> line (Jon).
> ---
> ---
>  Documentation/driver-api/cxl/conventions.rst  |   1 +
>  .../driver-api/cxl/conventions/cxl-atl.rst    | 174 ++++++++++++++++++
>  2 files changed, 175 insertions(+)
>  create mode 100644 Documentation/driver-api/cxl/conventions/cxl-atl.rst
> 
> diff --git a/Documentation/driver-api/cxl/conventions.rst b/Documentation/driver-api/cxl/conventions.rst
> index 53f31a229c8d..cf427afac58b 100644
> --- a/Documentation/driver-api/cxl/conventions.rst
> +++ b/Documentation/driver-api/cxl/conventions.rst
> @@ -8,4 +8,5 @@ Compute Express Link: Linux Conventions
>     :caption: Contents
>  
>     conventions/cxl-lmh.rst
> +   conventions/cxl-atl.rst
>     conventions/template.rst
> diff --git a/Documentation/driver-api/cxl/conventions/cxl-atl.rst b/Documentation/driver-api/cxl/conventions/cxl-atl.rst
> new file mode 100644
> index 000000000000..955263dcbb3a
> --- /dev/null
> +++ b/Documentation/driver-api/cxl/conventions/cxl-atl.rst
> @@ -0,0 +1,174 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +ACPI PRM CXL Address Translation
> +================================
> +
> +Document
> +--------
> +
> +CXL Revision 3.2, Version 1.0
> +
> +License
> +-------
> +
> +SPDX-License Identifier: CC-BY-4.0
> +
> +Creator/Contributors
> +--------------------
> +
> +- Robert Richter, AMD
> +
> +Summary of the Change
> +---------------------
> +
> +The CXL Fixed Memory Window Structure (CFMWS) describes zero or more
Structures describe (plural given zero or more)

Really trivial but why the short wrap?  Isn't it 80 chars for documentation?

> +Host Physical Address (HPA) windows that are associated with each CXL
> +Host Bridge. The HPA ranges of a CFMWS may include addresses that are

Hmm. This is a simplistic description of CFMWS given it's a many to many
relationship.  So in general would be something like

Host Physical Address (HPA) windows that are associated with a set of CXL
Host Bridges.

However, if this particular convention only applies to cases not interleaving
across multiple host bridges, perhaps state that at the top then this text
would be fine as it's a special case.

> +currently assigned to CXL.mem devices, or an OS may assign ranges from
> +an address window to a device.