Re: [PATCH v2 1/6] dt-bindings: iio: frequency: add adf41513

[Krzysztof Kozlowski <krzk@kernel.org>]

On Fri, Dec 19, 2025 at 12:34:48PM +0000, Rodrigo Alencar wrote:
> dt-bindings for ADF41513, an ultralow noise PLL frequency synthesizer that
> can be used to implement local oscillators (LOs) as high as 26.5 GHz.
> Most properties refer to existing PLL driver properties (e.g. ADF4350).

What is "existing PLL driver"? I know about motor drivers, but can you
drive PLL?

And how is ADF4350 related to this binding. I do not see ADF4350
compatible here at all. Describe hardware, a real one.


> 
> Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com>
> ---
>  .../bindings/iio/frequency/adi,adf41513.yaml       | 246 +++++++++++++++++++++
>  MAINTAINERS                                        |   7 +
>  2 files changed, 253 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml
> new file mode 100644
> index 000000000000..01ceb2a7d21b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml
> @@ -0,0 +1,246 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/frequency/adi,adf41513.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog Devices ADF41513 PLL Frequency Synthesizer
> +
> +maintainers:
> +  - Rodrigo Alencar <rodrigo.alencar@analog.com>
> +
> +description:
> +  The ADF41513 is an ultralow noise frequency synthesizer that can be used to
> +  implement local oscillators (LOs) as high as 26.5 GHz in the upconversion and
> +  downconversion sections of wireless receivers and transmitters. The ADF41510
> +  supports frequencies up to 10 GHz.
> +
> +  https://www.analog.com/en/products/adf41513.html
> +  https://www.analog.com/en/products/adf41510.html
> +
> +$ref: /schemas/spi/spi-peripheral-props.yaml#
> +
> +properties:
> +  compatible:
> +    enum:
> +      - adi,adf41510
> +      - adi,adf41513
> +
> +  reg:
> +    maxItems: 1
> +
> +  spi-max-frequency:
> +    maximum: 25000000
> +
> +  clocks:
> +    maxItems: 1
> +    description: Clock that provides the reference input frequency.
> +
> +  avdd1-supply:
> +    description: PFD and Up and Down Digital Driver Power Supply (3.3 V)
> +
> +  avdd2-supply:
> +    description: RF Buffer and Prescaler Power Supply (3.3 V)
> +
> +  avdd3-supply:
> +    description: N Divider Power Supply (3.3 V)
> +
> +  avdd4-supply:
> +    description: R Divider and Lock Detector Power Supply (3.3 V)
> +
> +  avdd5-supply:
> +    description: Sigma-Delta Modulator and SPI Power Supply (3.3 V)
> +
> +  vp-supply:
> +    description: Charge Pump Power Supply (3.3 V)
> +
> +  enable-gpios:
> +    description:
> +      GPIO that controls the chip enable pin. A logic low on this pin
> +      powers down the device and puts the charge pump output into
> +      three-state mode.
> +    maxItems: 1
> +
> +  lock-detect-gpios:
> +    description:
> +      GPIO for lock detect functionality. When configured for digital lock
> +      detect, this pin will output a logic high when the PLL is locked.
> +    maxItems: 1
> +
> +  adi,power-up-frequency:

Nothing improved.

You ignored comments, did not bother to respond to them and then sent
the same.

NAK

Best regards,
Krzysztof