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[2a00:1028:83b8:1e7a:3010:3bd6:8521:caf1]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4327778e27bsm66263511f8f.12.2026.01.05.01.51.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jan 2026 01:52:00 -0800 (PST) Date: Mon, 5 Jan 2026 10:51:58 +0100 From: Petr Tesarik To: "Michael S. Tsirkin" Cc: linux-kernel@vger.kernel.org, Cong Wang , Jonathan Corbet , Olivia Mackall , Herbert Xu , Jason Wang , Paolo Bonzini , Stefan Hajnoczi , Eugenio =?UTF-8?B?UMOpcmV6?= , "James E.J. Bottomley" , "Martin K. Petersen" , Gerd Hoffmann , Xuan Zhuo , Marek Szyprowski , Robin Murphy , Stefano Garzarella , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Leon Romanovsky , Jason Gunthorpe , Bartosz Golaszewski , linux-doc@vger.kernel.org, linux-crypto@vger.kernel.org, virtualization@lists.linux.dev, linux-scsi@vger.kernel.org, iommu@lists.linux.dev, kvm@vger.kernel.org, netdev@vger.kernel.org Subject: Re: [PATCH v2 04/15] docs: dma-api: document DMA_ATTR_CPU_CACHE_CLEAN Message-ID: <20260105105158.248b4dd2@mordecai> In-Reply-To: <0720b4be31c1b7a38edca67fd0c97983d2a56936.1767601130.git.mst@redhat.com> References: <0720b4be31c1b7a38edca67fd0c97983d2a56936.1767601130.git.mst@redhat.com> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.51; x86_64-suse-linux-gnu) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Mon, 5 Jan 2026 03:23:05 -0500 "Michael S. Tsirkin" wrote: > Document DMA_ATTR_CPU_CACHE_CLEAN as implemented in the > previous patch. > > Signed-off-by: Michael S. Tsirkin LGTM. I'm not formally a reviewer, but FWIW: Reviewed-by: Petr Tesarik > --- > Documentation/core-api/dma-attributes.rst | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/Documentation/core-api/dma-attributes.rst b/Documentation/core-api/dma-attributes.rst > index 0bdc2be65e57..1d7bfad73b1c 100644 > --- a/Documentation/core-api/dma-attributes.rst > +++ b/Documentation/core-api/dma-attributes.rst > @@ -148,3 +148,12 @@ DMA_ATTR_MMIO is appropriate. > For architectures that require cache flushing for DMA coherence > DMA_ATTR_MMIO will not perform any cache flushing. The address > provided must never be mapped cacheable into the CPU. > + > +DMA_ATTR_CPU_CACHE_CLEAN > +------------------------ > + > +This attribute indicates the CPU will not dirty any cacheline overlapping this > +DMA_FROM_DEVICE/DMA_BIDIRECTIONAL buffer while it is mapped. This allows > +multiple small buffers to safely share a cacheline without risk of data > +corruption, suppressing DMA debug warnings about overlapping mappings. > +All mappings sharing a cacheline should have this attribute.