* [PATCH v2 1/3] PCI: trace: Add PCI controller LTSSM transition tracepoint
2026-01-09 3:29 [PATCH v2 0/3] PCI Controller event and LTSSM tracepoint support Shawn Lin
@ 2026-01-09 3:29 ` Shawn Lin
2026-01-09 3:42 ` Steven Rostedt
2026-01-09 3:29 ` [PATCH v2 2/3] Documentation: tracing: Add PCI controller event documentation Shawn Lin
2026-01-09 3:29 ` [PATCH v2 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support Shawn Lin
2 siblings, 1 reply; 12+ messages in thread
From: Shawn Lin @ 2026-01-09 3:29 UTC (permalink / raw)
To: Manivannan Sadhasivam, Bjorn Helgaas
Cc: linux-rockchip, linux-pci, linux-trace-kernel, linux-doc,
Steven Rostedt, Masami Hiramatsu, Shawn Lin
Some platforms may provide LTSSM trace functionality, recording historical
LTSSM state transition information. This is very useful for debugging, such
as when certain devices cannot be recognized or link broken during test.
Implement the pci controller tracepoint for recording LTSSM and rate.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Changes in v2: None
drivers/pci/trace.c | 1 +
include/trace/events/pci_controller.h | 44 +++++++++++++++++++++++++++++++++++
2 files changed, 45 insertions(+)
create mode 100644 include/trace/events/pci_controller.h
diff --git a/drivers/pci/trace.c b/drivers/pci/trace.c
index cf11abc..c1da9d3 100644
--- a/drivers/pci/trace.c
+++ b/drivers/pci/trace.c
@@ -9,3 +9,4 @@
#define CREATE_TRACE_POINTS
#include <trace/events/pci.h>
+#include <trace/events/pci_controller.h>
diff --git a/include/trace/events/pci_controller.h b/include/trace/events/pci_controller.h
new file mode 100644
index 0000000..47d54c6
--- /dev/null
+++ b/include/trace/events/pci_controller.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM pci_controller
+
+#if !defined(_TRACE_HW_EVENT_PCI_CONTROLLER_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_HW_EVENT_PCI_CONTROLLER_H
+
+#include <uapi/linux/pci_regs.h>
+#include <linux/tracepoint.h>
+
+TRACE_EVENT(pcie_ltssm_state_transition,
+ TP_PROTO(const char *dev_name, const char *state, u32 rate),
+ TP_ARGS(dev_name, state, rate),
+
+ TP_STRUCT__entry(
+ __string(dev_name, dev_name)
+ __string(state, state)
+ __field(u32, rate)
+ ),
+
+ TP_fast_assign(
+ __assign_str(dev_name);
+ __assign_str(state);
+ __entry->rate = rate;
+ ),
+
+ TP_printk("dev: %s state: %s rate: %s",
+ __get_str(dev_name), __get_str(state),
+ __print_symbolic(__entry->rate,
+ { PCIE_SPEED_2_5GT, "2.5 GT/s" },
+ { PCIE_SPEED_5_0GT, "5.0 GT/s" },
+ { PCIE_SPEED_8_0GT, "8.0 GT/s" },
+ { PCIE_SPEED_16_0GT, "16.0 GT/s" },
+ { PCIE_SPEED_32_0GT, "32.0 GT/s" },
+ { PCIE_SPEED_64_0GT, "64.0 GT/s" },
+ { PCI_SPEED_UNKNOWN, "Unknown" }
+ )
+ )
+);
+
+#endif /* _TRACE_HW_EVENT_PCI_CONTROLLER_H */
+
+/* This part must be outside protection */
+#include <trace/define_trace.h>
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 1/3] PCI: trace: Add PCI controller LTSSM transition tracepoint
2026-01-09 3:29 ` [PATCH v2 1/3] PCI: trace: Add PCI controller LTSSM transition tracepoint Shawn Lin
@ 2026-01-09 3:42 ` Steven Rostedt
0 siblings, 0 replies; 12+ messages in thread
From: Steven Rostedt @ 2026-01-09 3:42 UTC (permalink / raw)
To: Shawn Lin
Cc: Manivannan Sadhasivam, Bjorn Helgaas, linux-rockchip, linux-pci,
linux-trace-kernel, linux-doc, Masami Hiramatsu
On Fri, 9 Jan 2026 11:29:47 +0800
Shawn Lin <shawn.lin@rock-chips.com> wrote:
> + TP_printk("dev: %s state: %s rate: %s",
> + __get_str(dev_name), __get_str(state),
> + __print_symbolic(__entry->rate,
> + { PCIE_SPEED_2_5GT, "2.5 GT/s" },
> + { PCIE_SPEED_5_0GT, "5.0 GT/s" },
> + { PCIE_SPEED_8_0GT, "8.0 GT/s" },
> + { PCIE_SPEED_16_0GT, "16.0 GT/s" },
> + { PCIE_SPEED_32_0GT, "32.0 GT/s" },
> + { PCIE_SPEED_64_0GT, "64.0 GT/s" },
> + { PCI_SPEED_UNKNOWN, "Unknown" }
As these values are all enums, you may want to add in this file:
TRACE_DEFINE_ENUM(PCIE_SPEED_2_5GT);
TRACE_DEFINE_ENUM(PCIE_SPEED_5_0GT);
[..]
TRACE_DEFINE_ENUM(PCIE_SPEED_UNKNOWN);
So that this can be parsed by user space tooling such as trace-cmd and
perf.
-- Steve
> + )
> + )
> +);
> +
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 2/3] Documentation: tracing: Add PCI controller event documentation
2026-01-09 3:29 [PATCH v2 0/3] PCI Controller event and LTSSM tracepoint support Shawn Lin
2026-01-09 3:29 ` [PATCH v2 1/3] PCI: trace: Add PCI controller LTSSM transition tracepoint Shawn Lin
@ 2026-01-09 3:29 ` Shawn Lin
2026-01-09 3:53 ` Bagas Sanjaya
` (3 more replies)
2026-01-09 3:29 ` [PATCH v2 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support Shawn Lin
2 siblings, 4 replies; 12+ messages in thread
From: Shawn Lin @ 2026-01-09 3:29 UTC (permalink / raw)
To: Manivannan Sadhasivam, Bjorn Helgaas
Cc: linux-rockchip, linux-pci, linux-trace-kernel, linux-doc,
Steven Rostedt, Masami Hiramatsu, Shawn Lin
The available tracepoint, pcie_ltssm_state_transition, monitors the LTSSM state
transistion for debugging purpose. Add description about it.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Changes in v2: None
Documentation/trace/events-pci-conotroller.rst | 41 ++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/trace/events-pci-conotroller.rst
diff --git a/Documentation/trace/events-pci-conotroller.rst b/Documentation/trace/events-pci-conotroller.rst
new file mode 100644
index 0000000..8253d00
--- /dev/null
+++ b/Documentation/trace/events-pci-conotroller.rst
@@ -0,0 +1,41 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+======================================
+Subsystem Trace Points: PCI Controller
+======================================
+
+Overview
+========
+The PCI controller tracing system provides tracepoints to monitor controller level
+information for debugging purpose. The events normally show up here:
+up here:
+
+ /sys/kernel/tracing/events/pci_controller
+
+Cf. include/trace/events/pci_controller.h for the events definitions.
+
+Available Tracepoints
+=====================
+
+pcie_ltssm_state_transition
+-----------------------
+
+Monitors PCIe LTSSM state transition including state and rate information
+::
+
+ pcie_ltssm_state_transition "dev: %s state: %s rate: %s\n"
+
+**Parameters**:
+
+* ``dev`` - PCIe root port name
+* ``state`` - PCIe LTSSM state
+* ``rate`` - PCIe bus speed
+
+**Example Usage**:
+
+ # Enable the tracepoint
+ echo 1 > /sys/kernel/debug/tracing/events/pci/pcie_ltssm_state_transition/enable
+
+ # Monitor events (the following output is generated when a device is linking)
+ cat /sys/kernel/debug/tracing/trace_pipe
+ kworker/0:0-9 [000] ..... 5.600221: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_EQ2 rate: 8.0 GT/s
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 2/3] Documentation: tracing: Add PCI controller event documentation
2026-01-09 3:29 ` [PATCH v2 2/3] Documentation: tracing: Add PCI controller event documentation Shawn Lin
@ 2026-01-09 3:53 ` Bagas Sanjaya
2026-01-09 5:19 ` Manivannan Sadhasivam
` (2 subsequent siblings)
3 siblings, 0 replies; 12+ messages in thread
From: Bagas Sanjaya @ 2026-01-09 3:53 UTC (permalink / raw)
To: Shawn Lin, Manivannan Sadhasivam, Bjorn Helgaas
Cc: linux-rockchip, linux-pci, linux-trace-kernel, linux-doc,
Steven Rostedt, Masami Hiramatsu
[-- Attachment #1: Type: text/plain, Size: 938 bytes --]
On Fri, Jan 09, 2026 at 11:29:48AM +0800, Shawn Lin wrote:
> Documentation/trace/events-pci-conotroller.rst | 41 ++++++++++++++++++++++++++
Missing toctree entry in Documentation/trace/index.rst.
> +Available Tracepoints
> +=====================
> +
> +pcie_ltssm_state_transition
> +-----------------------
Please match section underline length.
> +**Example Usage**:
> +
> + # Enable the tracepoint
> + echo 1 > /sys/kernel/debug/tracing/events/pci/pcie_ltssm_state_transition/enable
> +
> + # Monitor events (the following output is generated when a device is linking)
> + cat /sys/kernel/debug/tracing/trace_pipe
> + kworker/0:0-9 [000] ..... 5.600221: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_EQ2 rate: 8.0 GT/s
Wrap above example snippets in literal code block (use double colon).
Thanks.
--
An old man doll... just what I always wanted! - Clara
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 2/3] Documentation: tracing: Add PCI controller event documentation
2026-01-09 3:29 ` [PATCH v2 2/3] Documentation: tracing: Add PCI controller event documentation Shawn Lin
2026-01-09 3:53 ` Bagas Sanjaya
@ 2026-01-09 5:19 ` Manivannan Sadhasivam
2026-01-09 20:08 ` kernel test robot
2026-01-09 20:18 ` Bjorn Helgaas
3 siblings, 0 replies; 12+ messages in thread
From: Manivannan Sadhasivam @ 2026-01-09 5:19 UTC (permalink / raw)
To: Shawn Lin
Cc: Bjorn Helgaas, linux-rockchip, linux-pci, linux-trace-kernel,
linux-doc, Steven Rostedt, Masami Hiramatsu
On Fri, Jan 09, 2026 at 11:29:48AM +0800, Shawn Lin wrote:
> The available tracepoint, pcie_ltssm_state_transition, monitors the LTSSM state
> transistion for debugging purpose. Add description about it.
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> Changes in v2: None
>
> Documentation/trace/events-pci-conotroller.rst | 41 ++++++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
> create mode 100644 Documentation/trace/events-pci-conotroller.rst
>
> diff --git a/Documentation/trace/events-pci-conotroller.rst b/Documentation/trace/events-pci-conotroller.rst
> new file mode 100644
> index 0000000..8253d00
> --- /dev/null
> +++ b/Documentation/trace/events-pci-conotroller.rst
> @@ -0,0 +1,41 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +======================================
> +Subsystem Trace Points: PCI Controller
> +======================================
> +
> +Overview
> +========
> +The PCI controller tracing system provides tracepoints to monitor controller level
> +information for debugging purpose. The events normally show up here:
> +up here:
> +
> + /sys/kernel/tracing/events/pci_controller
> +
> +Cf. include/trace/events/pci_controller.h for the events definitions.
> +
> +Available Tracepoints
> +=====================
> +
> +pcie_ltssm_state_transition
> +-----------------------
> +
> +Monitors PCIe LTSSM state transition including state and rate information
> +::
> +
> + pcie_ltssm_state_transition "dev: %s state: %s rate: %s\n"
> +
> +**Parameters**:
> +
> +* ``dev`` - PCIe root port name
'PCIe controller instance'
> +* ``state`` - PCIe LTSSM state
> +* ``rate`` - PCIe bus speed
'PCIe data rate'
> +
> +**Example Usage**:
> +
> + # Enable the tracepoint
> + echo 1 > /sys/kernel/debug/tracing/events/pci/pcie_ltssm_state_transition/enable
/sys/kernel/debug/tracing/events/pci_controller/pcie_ltssm_state_transition/enable
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/3] Documentation: tracing: Add PCI controller event documentation
2026-01-09 3:29 ` [PATCH v2 2/3] Documentation: tracing: Add PCI controller event documentation Shawn Lin
2026-01-09 3:53 ` Bagas Sanjaya
2026-01-09 5:19 ` Manivannan Sadhasivam
@ 2026-01-09 20:08 ` kernel test robot
2026-01-09 20:18 ` Bjorn Helgaas
3 siblings, 0 replies; 12+ messages in thread
From: kernel test robot @ 2026-01-09 20:08 UTC (permalink / raw)
To: Shawn Lin, Manivannan Sadhasivam, Bjorn Helgaas
Cc: oe-kbuild-all, linux-rockchip, linux-pci, linux-trace-kernel,
linux-doc, Steven Rostedt, Masami Hiramatsu, Shawn Lin
Hi Shawn,
kernel test robot noticed the following build warnings:
[auto build test WARNING on pci/next]
[also build test WARNING on next-20260109]
[cannot apply to pci/for-linus mani-mhi/mhi-next trace/for-next linus/master v6.19-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Shawn-Lin/PCI-trace-Add-PCI-controller-LTSSM-transition-tracepoint/20260109-153843
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/1767929389-143957-3-git-send-email-shawn.lin%40rock-chips.com
patch subject: [PATCH v2 2/3] Documentation: tracing: Add PCI controller event documentation
reproduce: (https://download.01.org/0day-ci/archive/20260109/202601092104.0IlUz26P-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601092104.0IlUz26P-lkp@intel.com/
All warnings (new ones prefixed by >>):
WARNING: No kernel-doc for file ./include/linux/delay.h
ERROR: Cannot find file ./include/linux/delay.h
WARNING: No kernel-doc for file ./include/linux/delay.h
ERROR: Cannot find file ./include/linux/delay.h
WARNING: No kernel-doc for file ./include/linux/delay.h
>> Documentation/trace/events-pci-conotroller.rst:21: WARNING: Title underline too short.
--
ERROR: Cannot find file ./include/linux/mutex.h
ERROR: Cannot find file ./include/linux/mutex.h
WARNING: No kernel-doc for file ./include/linux/mutex.h
ERROR: Cannot find file ./include/linux/fwctl.h
WARNING: No kernel-doc for file ./include/linux/fwctl.h
>> Documentation/trace/events-pci-conotroller.rst: WARNING: document isn't included in any toctree [toc.not_included]
vim +21 Documentation/trace/events-pci-conotroller.rst
19
20 pcie_ltssm_state_transition
> 21 -----------------------
22
23 Monitors PCIe LTSSM state transition including state and rate information
24 ::
25
26 pcie_ltssm_state_transition "dev: %s state: %s rate: %s\n"
27
28 **Parameters**:
29
30 * ``dev`` - PCIe root port name
31 * ``state`` - PCIe LTSSM state
32 * ``rate`` - PCIe bus speed
33
34 **Example Usage**:
35
36 # Enable the tracepoint
37 echo 1 > /sys/kernel/debug/tracing/events/pci/pcie_ltssm_state_transition/enable
38
39 # Monitor events (the following output is generated when a device is linking)
40 cat /sys/kernel/debug/tracing/trace_pipe
> 41 kworker/0:0-9 [000] ..... 5.600221: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_EQ2 rate: 8.0 GT/s
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 2/3] Documentation: tracing: Add PCI controller event documentation
2026-01-09 3:29 ` [PATCH v2 2/3] Documentation: tracing: Add PCI controller event documentation Shawn Lin
` (2 preceding siblings ...)
2026-01-09 20:08 ` kernel test robot
@ 2026-01-09 20:18 ` Bjorn Helgaas
3 siblings, 0 replies; 12+ messages in thread
From: Bjorn Helgaas @ 2026-01-09 20:18 UTC (permalink / raw)
To: Shawn Lin
Cc: Manivannan Sadhasivam, Bjorn Helgaas, linux-rockchip, linux-pci,
linux-trace-kernel, linux-doc, Steven Rostedt, Masami Hiramatsu
On Fri, Jan 09, 2026 at 11:29:48AM +0800, Shawn Lin wrote:
> The available tracepoint, pcie_ltssm_state_transition, monitors the LTSSM state
> transistion for debugging purpose. Add description about it.
s/transistion/transition/
> Documentation/trace/events-pci-conotroller.rst | 41 ++++++++++++++++++++++++++
s/events-pci-conotroller.rst/events-pci-controller.rst/
> +The PCI controller tracing system provides tracepoints to monitor controller level
> +information for debugging purpose. The events normally show up here:
> +up here:
Wrap text to fit in 80 columns (unless it's a command line or similar
that shouldn't be split).
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support
2026-01-09 3:29 [PATCH v2 0/3] PCI Controller event and LTSSM tracepoint support Shawn Lin
2026-01-09 3:29 ` [PATCH v2 1/3] PCI: trace: Add PCI controller LTSSM transition tracepoint Shawn Lin
2026-01-09 3:29 ` [PATCH v2 2/3] Documentation: tracing: Add PCI controller event documentation Shawn Lin
@ 2026-01-09 3:29 ` Shawn Lin
2026-01-09 5:55 ` Manivannan Sadhasivam
2 siblings, 1 reply; 12+ messages in thread
From: Shawn Lin @ 2026-01-09 3:29 UTC (permalink / raw)
To: Manivannan Sadhasivam, Bjorn Helgaas
Cc: linux-rockchip, linux-pci, linux-trace-kernel, linux-doc,
Steven Rostedt, Masami Hiramatsu, Shawn Lin
Rockchip platforms provide a 64x4 bytes debug FIFO to trace the
LTSSM history. Any LTSSM change will be recorded. It's userful
for debug purpose, for example link failure, etc.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Changes in v2:
- use tracepoint
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 92 +++++++++++++++++++++++++++
1 file changed, 92 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 352f513..be9639aa 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -22,6 +22,8 @@
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
+#include <linux/workqueue.h>
+#include <trace/events/pci_controller.h>
#include "../../pci.h"
#include "pcie-designware.h"
@@ -73,6 +75,18 @@
#define PCIE_CLIENT_CDM_RASDES_TBA_L1_1 BIT(4)
#define PCIE_CLIENT_CDM_RASDES_TBA_L1_2 BIT(5)
+/* Debug FIFO information */
+#define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310
+#define PCIE_CLIENT_DBG_EN 0xffff0007
+#define PCIE_CLIENT_DBG_DIS 0xffff0000
+#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320
+#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324
+#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328
+#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c
+#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
+#define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
+#define PCIE_DBG_LTSSM_HISTORY_CNT 64
+
/* Hot Reset Control Register */
#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
#define PCIE_LTSSM_APP_DLY2_EN BIT(1)
@@ -96,6 +110,7 @@ struct rockchip_pcie {
struct irq_domain *irq_domain;
const struct rockchip_pcie_of_data *data;
bool supports_clkreq;
+ struct delayed_work trace_work;
};
struct rockchip_pcie_of_data {
@@ -206,6 +221,79 @@ static enum dw_pcie_ltssm rockchip_pcie_get_ltssm(struct dw_pcie *pci)
return rockchip_pcie_get_ltssm_reg(rockchip) & PCIE_LTSSM_STATUS_MASK;
}
+#ifdef CONFIG_TRACING
+static void rockchip_pcie_ltssm_trace_work(struct work_struct *work)
+{
+ struct rockchip_pcie *rockchip = container_of(work, struct rockchip_pcie,
+ trace_work.work);
+ struct dw_pcie *pci = &rockchip->pci;
+ enum dw_pcie_ltssm state;
+ u32 val, rate, l1ss, loop, prev_val = DW_PCIE_LTSSM_UNKNOWN;
+
+ for (loop = 0; loop < PCIE_DBG_LTSSM_HISTORY_CNT; loop++) {
+ val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_DBG_FIFO_STATUS);
+ rate = (val & GENMASK(22, 20)) >> 20;
+ l1ss = (val & GENMASK(10, 8)) >> 8;
+ val &= PCIE_LTSSM_STATUS_MASK;
+
+ /* Two consecutive identical LTSSM means invalid subsequent data */
+ if ((loop > 0 && val == prev_val) || val > DW_PCIE_LTSSM_RCVRY_EQ3)
+ break;
+
+ state = prev_val = val;
+ if (val == DW_PCIE_LTSSM_L1_IDLE) {
+ if (l1ss == 2)
+ state = DW_PCIE_LTSSM_L1_2;
+ else if (l1ss == 1)
+ state = DW_PCIE_LTSSM_L1_1;
+ }
+
+ trace_pcie_ltssm_state_transition(dev_name(pci->dev),
+ dw_pcie_ltssm_status_string(state),
+ ((rate + 1) > pci->max_link_speed) ?
+ PCI_SPEED_UNKNOWN : PCIE_SPEED_2_5GT + rate);
+ }
+
+ schedule_delayed_work(&rockchip->trace_work, msecs_to_jiffies(5000));
+}
+
+static void rockchip_pcie_ltssm_trace(struct rockchip_pcie *rockchip,
+ bool en)
+{
+ if (en) {
+ rockchip_pcie_writel_apb(rockchip,
+ PCIE_CLIENT_DBG_TRANSITION_DATA,
+ PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0);
+ rockchip_pcie_writel_apb(rockchip,
+ PCIE_CLIENT_DBG_TRANSITION_DATA,
+ PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1);
+ rockchip_pcie_writel_apb(rockchip,
+ PCIE_CLIENT_DBG_TRANSITION_DATA,
+ PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0);
+ rockchip_pcie_writel_apb(rockchip,
+ PCIE_CLIENT_DBG_TRANSITION_DATA,
+ PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1);
+ rockchip_pcie_writel_apb(rockchip,
+ PCIE_CLIENT_DBG_EN,
+ PCIE_CLIENT_DBG_FIFO_MODE_CON);
+
+ INIT_DELAYED_WORK(&rockchip->trace_work,
+ rockchip_pcie_ltssm_trace_work);
+ schedule_delayed_work(&rockchip->trace_work, 0);
+ } else {
+ rockchip_pcie_writel_apb(rockchip,
+ PCIE_CLIENT_DBG_DIS,
+ PCIE_CLIENT_DBG_FIFO_MODE_CON);
+ cancel_delayed_work_sync(&rockchip->trace_work);
+ }
+}
+#else
+static void rockchip_pcie_ltssm_trace(struct rockchip_pcie *rockchip,
+ bool en)
+{
+}
+#endif
+
static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
{
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
@@ -289,6 +377,9 @@ static int rockchip_pcie_start_link(struct dw_pcie *pci)
* 100us as we don't know how long should the device need to reset.
*/
msleep(PCIE_T_PVPERL_MS);
+
+ rockchip_pcie_ltssm_trace(rockchip, true);
+
gpiod_set_value_cansleep(rockchip->rst_gpio, 1);
return 0;
@@ -299,6 +390,7 @@ static void rockchip_pcie_stop_link(struct dw_pcie *pci)
struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
rockchip_pcie_disable_ltssm(rockchip);
+ rockchip_pcie_ltssm_trace(rockchip, false);
}
static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support
2026-01-09 3:29 ` [PATCH v2 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support Shawn Lin
@ 2026-01-09 5:55 ` Manivannan Sadhasivam
2026-01-09 6:22 ` Shawn Lin
0 siblings, 1 reply; 12+ messages in thread
From: Manivannan Sadhasivam @ 2026-01-09 5:55 UTC (permalink / raw)
To: Shawn Lin
Cc: Bjorn Helgaas, linux-rockchip, linux-pci, linux-trace-kernel,
linux-doc, Steven Rostedt, Masami Hiramatsu
On Fri, Jan 09, 2026 at 11:29:49AM +0800, Shawn Lin wrote:
> Rockchip platforms provide a 64x4 bytes debug FIFO to trace the
> LTSSM history. Any LTSSM change will be recorded. It's userful
> for debug purpose, for example link failure, etc.
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> Changes in v2:
> - use tracepoint
>
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 92 +++++++++++++++++++++++++++
> 1 file changed, 92 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index 352f513..be9639aa 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -22,6 +22,8 @@
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> #include <linux/reset.h>
> +#include <linux/workqueue.h>
> +#include <trace/events/pci_controller.h>
>
> #include "../../pci.h"
> #include "pcie-designware.h"
> @@ -73,6 +75,18 @@
> #define PCIE_CLIENT_CDM_RASDES_TBA_L1_1 BIT(4)
> #define PCIE_CLIENT_CDM_RASDES_TBA_L1_2 BIT(5)
>
> +/* Debug FIFO information */
> +#define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310
> +#define PCIE_CLIENT_DBG_EN 0xffff0007
> +#define PCIE_CLIENT_DBG_DIS 0xffff0000
> +#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320
> +#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324
> +#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328
> +#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c
> +#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
> +#define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
> +#define PCIE_DBG_LTSSM_HISTORY_CNT 64
> +
> /* Hot Reset Control Register */
> #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
> #define PCIE_LTSSM_APP_DLY2_EN BIT(1)
> @@ -96,6 +110,7 @@ struct rockchip_pcie {
> struct irq_domain *irq_domain;
> const struct rockchip_pcie_of_data *data;
> bool supports_clkreq;
> + struct delayed_work trace_work;
> };
>
> struct rockchip_pcie_of_data {
> @@ -206,6 +221,79 @@ static enum dw_pcie_ltssm rockchip_pcie_get_ltssm(struct dw_pcie *pci)
> return rockchip_pcie_get_ltssm_reg(rockchip) & PCIE_LTSSM_STATUS_MASK;
> }
>
> +#ifdef CONFIG_TRACING
> +static void rockchip_pcie_ltssm_trace_work(struct work_struct *work)
> +{
> + struct rockchip_pcie *rockchip = container_of(work, struct rockchip_pcie,
> + trace_work.work);
> + struct dw_pcie *pci = &rockchip->pci;
> + enum dw_pcie_ltssm state;
> + u32 val, rate, l1ss, loop, prev_val = DW_PCIE_LTSSM_UNKNOWN;
Reverse Xmas order please.
> +
> + for (loop = 0; loop < PCIE_DBG_LTSSM_HISTORY_CNT; loop++) {
s/loop/i?
> + val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_DBG_FIFO_STATUS);
> + rate = (val & GENMASK(22, 20)) >> 20;
> + l1ss = (val & GENMASK(10, 8)) >> 8;
> + val &= PCIE_LTSSM_STATUS_MASK;
Can you use FIELD_ macros here?
> +
> + /* Two consecutive identical LTSSM means invalid subsequent data */
Interesting. Does the hardware maintain a counter to track the reads? So once
you break out of the loop and read it after 5s, you'll start from where you left
i.e., the duplicate entry or from the start of the counter again?
> + if ((loop > 0 && val == prev_val) || val > DW_PCIE_LTSSM_RCVRY_EQ3)
> + break;
> +
> + state = prev_val = val;
> + if (val == DW_PCIE_LTSSM_L1_IDLE) {
> + if (l1ss == 2)
> + state = DW_PCIE_LTSSM_L1_2;
> + else if (l1ss == 1)
> + state = DW_PCIE_LTSSM_L1_1;
I believe L1.0 is not supported.
> + }
> +
> + trace_pcie_ltssm_state_transition(dev_name(pci->dev),
> + dw_pcie_ltssm_status_string(state),
> + ((rate + 1) > pci->max_link_speed) ?
> + PCI_SPEED_UNKNOWN : PCIE_SPEED_2_5GT + rate);
> + }
> +
> + schedule_delayed_work(&rockchip->trace_work, msecs_to_jiffies(5000));
> +}
> +
> +static void rockchip_pcie_ltssm_trace(struct rockchip_pcie *rockchip,
> + bool en)
s/en/enable
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support
2026-01-09 5:55 ` Manivannan Sadhasivam
@ 2026-01-09 6:22 ` Shawn Lin
2026-01-09 7:33 ` Manivannan Sadhasivam
0 siblings, 1 reply; 12+ messages in thread
From: Shawn Lin @ 2026-01-09 6:22 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: shawn.lin, Bjorn Helgaas, linux-rockchip, linux-pci,
linux-trace-kernel, linux-doc, Steven Rostedt, Masami Hiramatsu
在 2026/01/09 星期五 13:55, Manivannan Sadhasivam 写道:
> On Fri, Jan 09, 2026 at 11:29:49AM +0800, Shawn Lin wrote:
>> Rockchip platforms provide a 64x4 bytes debug FIFO to trace the
>> LTSSM history. Any LTSSM change will be recorded. It's userful
>> for debug purpose, for example link failure, etc.
>>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>> ---
>>
>> Changes in v2:
>> - use tracepoint
>>
>> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 92 +++++++++++++++++++++++++++
>> 1 file changed, 92 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
>> index 352f513..be9639aa 100644
>> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
>> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
>> @@ -22,6 +22,8 @@
>> #include <linux/platform_device.h>
>> #include <linux/regmap.h>
>> #include <linux/reset.h>
>> +#include <linux/workqueue.h>
>> +#include <trace/events/pci_controller.h>
>>
>> #include "../../pci.h"
>> #include "pcie-designware.h"
>> @@ -73,6 +75,18 @@
>> #define PCIE_CLIENT_CDM_RASDES_TBA_L1_1 BIT(4)
>> #define PCIE_CLIENT_CDM_RASDES_TBA_L1_2 BIT(5)
>>
>> +/* Debug FIFO information */
>> +#define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310
>> +#define PCIE_CLIENT_DBG_EN 0xffff0007
>> +#define PCIE_CLIENT_DBG_DIS 0xffff0000
>> +#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320
>> +#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324
>> +#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328
>> +#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c
>> +#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
>> +#define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
>> +#define PCIE_DBG_LTSSM_HISTORY_CNT 64
>> +
>> /* Hot Reset Control Register */
>> #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
>> #define PCIE_LTSSM_APP_DLY2_EN BIT(1)
>> @@ -96,6 +110,7 @@ struct rockchip_pcie {
>> struct irq_domain *irq_domain;
>> const struct rockchip_pcie_of_data *data;
>> bool supports_clkreq;
>> + struct delayed_work trace_work;
>> };
>>
>> struct rockchip_pcie_of_data {
>> @@ -206,6 +221,79 @@ static enum dw_pcie_ltssm rockchip_pcie_get_ltssm(struct dw_pcie *pci)
>> return rockchip_pcie_get_ltssm_reg(rockchip) & PCIE_LTSSM_STATUS_MASK;
>> }
>>
>> +#ifdef CONFIG_TRACING
>> +static void rockchip_pcie_ltssm_trace_work(struct work_struct *work)
>> +{
>> + struct rockchip_pcie *rockchip = container_of(work, struct rockchip_pcie,
>> + trace_work.work);
>> + struct dw_pcie *pci = &rockchip->pci;
>> + enum dw_pcie_ltssm state;
>> + u32 val, rate, l1ss, loop, prev_val = DW_PCIE_LTSSM_UNKNOWN;
>
> Reverse Xmas order please.
>
>> +
>> + for (loop = 0; loop < PCIE_DBG_LTSSM_HISTORY_CNT; loop++) {
>
> s/loop/i?
>
>> + val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_DBG_FIFO_STATUS);
>> + rate = (val & GENMASK(22, 20)) >> 20;
>> + l1ss = (val & GENMASK(10, 8)) >> 8;
>> + val &= PCIE_LTSSM_STATUS_MASK;
>
> Can you use FIELD_ macros here?
>
>> +
>> + /* Two consecutive identical LTSSM means invalid subsequent data */
>
> Interesting. Does the hardware maintain a counter to track the reads? So once
> you break out of the loop and read it after 5s, you'll start from where you left
> i.e., the duplicate entry or from the start of the counter again?
>
Yes, the ring FIFO maintains counters for recording both of
last-read-point for user to continue to read, and last-valid-point for
HW to
continue to update transition state. So we could start from where we
left.
>> + if ((loop > 0 && val == prev_val) || val > DW_PCIE_LTSSM_RCVRY_EQ3)
>> + break;
>> +
>> + state = prev_val = val;
>> + if (val == DW_PCIE_LTSSM_L1_IDLE) {
>> + if (l1ss == 2)
>> + state = DW_PCIE_LTSSM_L1_2;
>> + else if (l1ss == 1)
>> + state = DW_PCIE_LTSSM_L1_1;
>
> I believe L1.0 is not supported.
>
I'm not sure I follow this comment. state is DW_PCIE_LTSSM_L1_IDLE
（L1.0） if l1ss is neither 1 nor 2.
>> + }
>> +
>> + trace_pcie_ltssm_state_transition(dev_name(pci->dev),
>> + dw_pcie_ltssm_status_string(state),
>> + ((rate + 1) > pci->max_link_speed) ?
>> + PCI_SPEED_UNKNOWN : PCIE_SPEED_2_5GT + rate);
>> + }
>> +
>> + schedule_delayed_work(&rockchip->trace_work, msecs_to_jiffies(5000));
>> +}
>> +
>> +static void rockchip_pcie_ltssm_trace(struct rockchip_pcie *rockchip,
>> + bool en)
>
> s/en/enable
>
> - Mani
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support
2026-01-09 6:22 ` Shawn Lin
@ 2026-01-09 7:33 ` Manivannan Sadhasivam
0 siblings, 0 replies; 12+ messages in thread
From: Manivannan Sadhasivam @ 2026-01-09 7:33 UTC (permalink / raw)
To: Shawn Lin
Cc: Bjorn Helgaas, linux-rockchip, linux-pci, linux-trace-kernel,
linux-doc, Steven Rostedt, Masami Hiramatsu
On Fri, Jan 09, 2026 at 02:22:10PM +0800, Shawn Lin wrote:
> 在 2026/01/09 星期五 13:55, Manivannan Sadhasivam 写道:
> > On Fri, Jan 09, 2026 at 11:29:49AM +0800, Shawn Lin wrote:
> > > Rockchip platforms provide a 64x4 bytes debug FIFO to trace the
> > > LTSSM history. Any LTSSM change will be recorded. It's userful
> > > for debug purpose, for example link failure, etc.
> > >
> > > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> > > ---
> > >
> > > Changes in v2:
> > > - use tracepoint
> > >
> > > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 92 +++++++++++++++++++++++++++
> > > 1 file changed, 92 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > > index 352f513..be9639aa 100644
> > > --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > > @@ -22,6 +22,8 @@
> > > #include <linux/platform_device.h>
> > > #include <linux/regmap.h>
> > > #include <linux/reset.h>
> > > +#include <linux/workqueue.h>
> > > +#include <trace/events/pci_controller.h>
> > > #include "../../pci.h"
> > > #include "pcie-designware.h"
> > > @@ -73,6 +75,18 @@
> > > #define PCIE_CLIENT_CDM_RASDES_TBA_L1_1 BIT(4)
> > > #define PCIE_CLIENT_CDM_RASDES_TBA_L1_2 BIT(5)
> > > +/* Debug FIFO information */
> > > +#define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310
> > > +#define PCIE_CLIENT_DBG_EN 0xffff0007
> > > +#define PCIE_CLIENT_DBG_DIS 0xffff0000
> > > +#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320
> > > +#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324
> > > +#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328
> > > +#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c
> > > +#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
> > > +#define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
> > > +#define PCIE_DBG_LTSSM_HISTORY_CNT 64
> > > +
> > > /* Hot Reset Control Register */
> > > #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
> > > #define PCIE_LTSSM_APP_DLY2_EN BIT(1)
> > > @@ -96,6 +110,7 @@ struct rockchip_pcie {
> > > struct irq_domain *irq_domain;
> > > const struct rockchip_pcie_of_data *data;
> > > bool supports_clkreq;
> > > + struct delayed_work trace_work;
> > > };
> > > struct rockchip_pcie_of_data {
> > > @@ -206,6 +221,79 @@ static enum dw_pcie_ltssm rockchip_pcie_get_ltssm(struct dw_pcie *pci)
> > > return rockchip_pcie_get_ltssm_reg(rockchip) & PCIE_LTSSM_STATUS_MASK;
> > > }
> > > +#ifdef CONFIG_TRACING
> > > +static void rockchip_pcie_ltssm_trace_work(struct work_struct *work)
> > > +{
> > > + struct rockchip_pcie *rockchip = container_of(work, struct rockchip_pcie,
> > > + trace_work.work);
> > > + struct dw_pcie *pci = &rockchip->pci;
> > > + enum dw_pcie_ltssm state;
> > > + u32 val, rate, l1ss, loop, prev_val = DW_PCIE_LTSSM_UNKNOWN;
> >
> > Reverse Xmas order please.
> >
> > > +
> > > + for (loop = 0; loop < PCIE_DBG_LTSSM_HISTORY_CNT; loop++) {
> >
> > s/loop/i?
> >
> > > + val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_DBG_FIFO_STATUS);
> > > + rate = (val & GENMASK(22, 20)) >> 20;
> > > + l1ss = (val & GENMASK(10, 8)) >> 8;
> > > + val &= PCIE_LTSSM_STATUS_MASK;
> >
> > Can you use FIELD_ macros here?
> >
> > > +
> > > + /* Two consecutive identical LTSSM means invalid subsequent data */
> >
> > Interesting. Does the hardware maintain a counter to track the reads? So once
> > you break out of the loop and read it after 5s, you'll start from where you left
> > i.e., the duplicate entry or from the start of the counter again?
> >
>
> Yes, the ring FIFO maintains counters for recording both of last-read-point
> for user to continue to read, and last-valid-point for HW to
> continue to update transition state. So we could start from where we
> left.
>
Ok. Thanks for clarification. It'd be worth to add it to the existing comment.
> > > + if ((loop > 0 && val == prev_val) || val > DW_PCIE_LTSSM_RCVRY_EQ3)
> > > + break;
> > > +
> > > + state = prev_val = val;
> > > + if (val == DW_PCIE_LTSSM_L1_IDLE) {
> > > + if (l1ss == 2)
> > > + state = DW_PCIE_LTSSM_L1_2;
> > > + else if (l1ss == 1)
> > > + state = DW_PCIE_LTSSM_L1_1;
> >
> > I believe L1.0 is not supported.
> >
>
> I'm not sure I follow this comment. state is DW_PCIE_LTSSM_L1_IDLE
> （L1.0） if l1ss is neither 1 nor 2.
>
Ah ok. It was not clear that L1_IDLE is L1.0
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 12+ messages in thread