* [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees
@ 2026-01-14 23:18 Guodong Xu
2026-01-14 23:18 ` [PATCH v2 1/4] Documentation: riscv: uabi: Clarify ISA spec version for canonical order Guodong Xu
` (6 more replies)
0 siblings, 7 replies; 14+ messages in thread
From: Guodong Xu @ 2026-01-14 23:18 UTC (permalink / raw)
To: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Conor Dooley, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Chen Wang, Inochi Amaoto, Yixun Lan,
Conor Dooley
Cc: Junhui Liu, linux-doc, linux-riscv, linux-kernel, devicetree,
sophgo, spacemit, Guodong Xu
The RISC-V "b" (Bit-manipulation) extension was ratified in April 2024,
much later than its component extensions zba/zbb/zbs (June 2021). Recent
updates to the device tree bindings [2] enforce that when all three
component extensions are present, "b" must also be specified. Related
discussion can also be found in [1].
Patch 1 clarifies the ISA spec version for canonical ordering in uabi.rst.
It is a trivial update, but can help readers reference the correct
document version. Acked-by Paul Walmsley in v1.
Patch 2, 3 and 4 adds "b" after "c" in 3 different device tree files
respectivly, anlogic, sophgo and spacemit, fixing the related dtbs_check
warnings.
This patchset is based on top of linux-next, tag: next-20260109, and
depends on [2].
Link: https://lore.kernel.org/all/20251230-imprison-sleet-6b5a1e26d34b@spud/ [1]
Link: https://lore.kernel.org/all/20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com/ [2]
Changes in v2:
- Patch 1: Add Acked-by from Paul Walmsley.
- Patch 2/3/4: These are splits from the v1 Patch 2. Split into three
different patches for each SoC.
- Link to v1: https://lore.kernel.org/r/20260113-adding-b-dtsi-v1-0-22d6e55d19df@riscstar.com
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
Guodong Xu (4):
Documentation: riscv: uabi: Clarify ISA spec version for canonical order
riscv: dts: anlogic: dr1v90: Add "b" ISA extension
riscv: dts: sophgo: sg2044: Add "b" ISA extension
riscv: dts: spacemit: k1: Add "b" ISA extension
Documentation/arch/riscv/uabi.rst | 4 +-
arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 5 +-
arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 256 ++++++++++++++--------------
arch/riscv/boot/dts/spacemit/k1.dtsi | 32 ++--
4 files changed, 150 insertions(+), 147 deletions(-)
---
base-commit: 31d167f54de93f14fa8e4bc6cbc4adaf7019fd94
change-id: 20260113-adding-b-dtsi-148714533f07
prerequisite-message-id: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com>
prerequisite-patch-id: 0c859b4d131b3360875c795c6148c6176b55fb91
prerequisite-patch-id: 2ed98dc1ab0f5ed923cc252415c345dc8caf6f17
prerequisite-patch-id: 1be1a031763fac029076a768f012af31e455be66
prerequisite-patch-id: 21bb8387c946e050910440e7a7622305d46d946d
prerequisite-patch-id: f3bdc2c74b230663710086bd770a755d56cb8b9c
prerequisite-patch-id: 1f162c02f8bdb5bbc8ce52ead4fcb76258f5c2b9
prerequisite-patch-id: 76e1ff26c2f1fe4019cfa574942b568000e6ca1f
prerequisite-patch-id: 77ddc9e5dc85495adc803cdc605bdda2ddc7fa47
prerequisite-patch-id: a75c798383b46a14d40436357c769c3671184768
prerequisite-patch-id: 781fc10dcae2c38c84c25bee887ef7474786dd36
prerequisite-patch-id: 5be5d3e62aa73024bf9e1de6aad155be6d618f40
Best regards,
--
Guodong Xu <guodong@riscstar.com>
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v2 1/4] Documentation: riscv: uabi: Clarify ISA spec version for canonical order 2026-01-14 23:18 [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees Guodong Xu @ 2026-01-14 23:18 ` Guodong Xu 2026-01-15 0:10 ` Paul Walmsley 2026-01-14 23:18 ` [PATCH v2 2/4] riscv: dts: anlogic: dr1v90: Add "b" ISA extension Guodong Xu ` (5 subsequent siblings) 6 siblings, 1 reply; 14+ messages in thread From: Guodong Xu @ 2026-01-14 23:18 UTC (permalink / raw) To: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Chen Wang, Inochi Amaoto, Yixun Lan, Conor Dooley Cc: Junhui Liu, linux-doc, linux-riscv, linux-kernel, devicetree, sophgo, spacemit, Guodong Xu Specify that chapter 27 refers to version 20191213 of the RISC-V ISA Unprivileged Architecture. The chapter numbering differs across specification versions - for example, in version 20250508, the ISA Extension Naming Conventions is chapter 36, not chapter 27. Historical versions of the RISC-V specification can be found via Link [1]. Acked-by: Paul Walmsley <pjw@kernel.org> Link: https://riscv.org/specifications/ratified/ [1] Fixes: f07b2b3f9d47 ("Documentation: riscv: add a section about ISA string ordering in /proc/cpuinfo") Signed-off-by: Guodong Xu <guodong@riscstar.com> --- v2: Add Acked-by from Paul. --- Documentation/arch/riscv/uabi.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/riscv/uabi.rst b/Documentation/arch/riscv/uabi.rst index 243e40062e34..0c5299e00762 100644 --- a/Documentation/arch/riscv/uabi.rst +++ b/Documentation/arch/riscv/uabi.rst @@ -7,7 +7,9 @@ ISA string ordering in /proc/cpuinfo ------------------------------------ The canonical order of ISA extension names in the ISA string is defined in -chapter 27 of the unprivileged specification. +Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA +(Document Version 20191213). + The specification uses vague wording, such as should, when it comes to ordering, so for our purposes the following rules apply: -- 2.43.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/4] Documentation: riscv: uabi: Clarify ISA spec version for canonical order 2026-01-14 23:18 ` [PATCH v2 1/4] Documentation: riscv: uabi: Clarify ISA spec version for canonical order Guodong Xu @ 2026-01-15 0:10 ` Paul Walmsley 0 siblings, 0 replies; 14+ messages in thread From: Paul Walmsley @ 2026-01-15 0:10 UTC (permalink / raw) To: Guodong Xu Cc: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Chen Wang, Inochi Amaoto, Yixun Lan, Conor Dooley, Junhui Liu, linux-doc, linux-riscv, linux-kernel, devicetree, sophgo, spacemit On Thu, 15 Jan 2026, Guodong Xu wrote: > Specify that chapter 27 refers to version 20191213 of the RISC-V ISA > Unprivileged Architecture. The chapter numbering differs across > specification versions - for example, in version 20250508, the ISA > Extension Naming Conventions is chapter 36, not chapter 27. > > Historical versions of the RISC-V specification can be found via Link [1]. > > Acked-by: Paul Walmsley <pjw@kernel.org> > Link: https://riscv.org/specifications/ratified/ [1] > Fixes: f07b2b3f9d47 ("Documentation: riscv: add a section about ISA string ordering in /proc/cpuinfo") > Signed-off-by: Guodong Xu <guodong@riscstar.com> Thanks, queued for v6.19-rc fixes. - Paul ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 2/4] riscv: dts: anlogic: dr1v90: Add "b" ISA extension 2026-01-14 23:18 [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees Guodong Xu 2026-01-14 23:18 ` [PATCH v2 1/4] Documentation: riscv: uabi: Clarify ISA spec version for canonical order Guodong Xu @ 2026-01-14 23:18 ` Guodong Xu 2026-01-15 2:25 ` Junhui Liu 2026-01-14 23:18 ` [PATCH v2 3/4] riscv: dts: sophgo: sg2044: " Guodong Xu ` (4 subsequent siblings) 6 siblings, 1 reply; 14+ messages in thread From: Guodong Xu @ 2026-01-14 23:18 UTC (permalink / raw) To: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Chen Wang, Inochi Amaoto, Yixun Lan, Conor Dooley Cc: Junhui Liu, linux-doc, linux-riscv, linux-kernel, devicetree, sophgo, spacemit, Guodong Xu "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update dr1v90.dtsi to conform to this rule. Line balancing is performed to improve readability. Signed-off-by: Guodong Xu <guodong@riscstar.com> --- v2: New patch, a split from the Patch 2 in v1. This patch is for Anlogic dr1v90. --- arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi index a5d0765ade32..9fe183f5f5c8 100644 --- a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi +++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi @@ -27,8 +27,9 @@ cpu@0 { mmu-type = "riscv,sv39"; reg = <0>; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc", - "zbkc", "zbs", "zicntr", "zicsr", "zifencei", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", + "zba", "zbb", "zbc", "zbkc", "zbs", + "zicntr", "zicsr", "zifencei", "zihintpause", "zihpm"; cpu0_intc: interrupt-controller { -- 2.43.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/4] riscv: dts: anlogic: dr1v90: Add "b" ISA extension 2026-01-14 23:18 ` [PATCH v2 2/4] riscv: dts: anlogic: dr1v90: Add "b" ISA extension Guodong Xu @ 2026-01-15 2:25 ` Junhui Liu 0 siblings, 0 replies; 14+ messages in thread From: Junhui Liu @ 2026-01-15 2:25 UTC (permalink / raw) To: Guodong Xu, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Chen Wang, Inochi Amaoto, Yixun Lan, Conor Dooley Cc: Junhui Liu, linux-doc, linux-riscv, linux-kernel, devicetree, sophgo, spacemit Hi Guodong, On Thu Jan 15, 2026 at 7:18 AM CST, Guodong Xu wrote: > "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs > (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency > checking rule is now enforced, which requires that when zba, zbb, and zbs > are all specified, "b" must be added as well. Failing to do this will > cause dtbs_check schema check warnings. > > According to uabi.rst, as a single-letter extension, "b" should be added > after "c" in canonical order. > > Update dr1v90.dtsi to conform to this rule. Line balancing is performed > to improve readability. > > Signed-off-by: Guodong Xu <guodong@riscstar.com> Reviewed-by: Junhui Liu <junhui.liu@pigmoral.tech> -- Best regards, Junhui Liu ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 3/4] riscv: dts: sophgo: sg2044: Add "b" ISA extension 2026-01-14 23:18 [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees Guodong Xu 2026-01-14 23:18 ` [PATCH v2 1/4] Documentation: riscv: uabi: Clarify ISA spec version for canonical order Guodong Xu 2026-01-14 23:18 ` [PATCH v2 2/4] riscv: dts: anlogic: dr1v90: Add "b" ISA extension Guodong Xu @ 2026-01-14 23:18 ` Guodong Xu 2026-01-15 0:28 ` Inochi Amaoto 2026-01-14 23:19 ` [PATCH v2 4/4] riscv: dts: spacemit: k1: " Guodong Xu ` (3 subsequent siblings) 6 siblings, 1 reply; 14+ messages in thread From: Guodong Xu @ 2026-01-14 23:18 UTC (permalink / raw) To: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Chen Wang, Inochi Amaoto, Yixun Lan, Conor Dooley Cc: Junhui Liu, linux-doc, linux-riscv, linux-kernel, devicetree, sophgo, spacemit, Guodong Xu "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update sg2044-cpus.dtsi to conform to this rule. Signed-off-by: Guodong Xu <guodong@riscstar.com> --- v2: New patch, a split from the Patch 2 in v1. This patch is for Sophgo sg2044. --- arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 256 ++++++++++++++-------------- 1 file changed, 128 insertions(+), 128 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi index 523799a1a8b8..3135409c2149 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi @@ -24,10 +24,10 @@ cpu0: cpu@0 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -60,10 +60,10 @@ cpu1: cpu@1 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -96,10 +96,10 @@ cpu2: cpu@2 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -132,10 +132,10 @@ cpu3: cpu@3 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -168,10 +168,10 @@ cpu4: cpu@4 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -204,10 +204,10 @@ cpu5: cpu@5 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -240,10 +240,10 @@ cpu6: cpu@6 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -276,10 +276,10 @@ cpu7: cpu@7 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -312,10 +312,10 @@ cpu8: cpu@8 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -348,10 +348,10 @@ cpu9: cpu@9 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -384,10 +384,10 @@ cpu10: cpu@10 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -420,10 +420,10 @@ cpu11: cpu@11 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -456,10 +456,10 @@ cpu12: cpu@12 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -492,10 +492,10 @@ cpu13: cpu@13 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -528,10 +528,10 @@ cpu14: cpu@14 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -564,10 +564,10 @@ cpu15: cpu@15 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -600,10 +600,10 @@ cpu16: cpu@16 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -636,10 +636,10 @@ cpu17: cpu@17 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -672,10 +672,10 @@ cpu18: cpu@18 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -708,10 +708,10 @@ cpu19: cpu@19 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -744,10 +744,10 @@ cpu20: cpu@20 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -780,10 +780,10 @@ cpu21: cpu@21 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -816,10 +816,10 @@ cpu22: cpu@22 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -852,10 +852,10 @@ cpu23: cpu@23 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -888,10 +888,10 @@ cpu24: cpu@24 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -924,10 +924,10 @@ cpu25: cpu@25 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -960,10 +960,10 @@ cpu26: cpu@26 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -996,10 +996,10 @@ cpu27: cpu@27 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1032,10 +1032,10 @@ cpu28: cpu@28 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1068,10 +1068,10 @@ cpu29: cpu@29 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1104,10 +1104,10 @@ cpu30: cpu@30 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1140,10 +1140,10 @@ cpu31: cpu@31 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1176,10 +1176,10 @@ cpu32: cpu@32 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1212,10 +1212,10 @@ cpu33: cpu@33 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1248,10 +1248,10 @@ cpu34: cpu@34 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1284,10 +1284,10 @@ cpu35: cpu@35 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1320,10 +1320,10 @@ cpu36: cpu@36 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1356,10 +1356,10 @@ cpu37: cpu@37 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1392,10 +1392,10 @@ cpu38: cpu@38 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1428,10 +1428,10 @@ cpu39: cpu@39 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1464,10 +1464,10 @@ cpu40: cpu@40 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1500,10 +1500,10 @@ cpu41: cpu@41 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1536,10 +1536,10 @@ cpu42: cpu@42 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1572,10 +1572,10 @@ cpu43: cpu@43 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1608,10 +1608,10 @@ cpu44: cpu@44 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1644,10 +1644,10 @@ cpu45: cpu@45 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1680,10 +1680,10 @@ cpu46: cpu@46 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1716,10 +1716,10 @@ cpu47: cpu@47 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1752,10 +1752,10 @@ cpu48: cpu@48 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1788,10 +1788,10 @@ cpu49: cpu@49 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1824,10 +1824,10 @@ cpu50: cpu@50 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1860,10 +1860,10 @@ cpu51: cpu@51 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1896,10 +1896,10 @@ cpu52: cpu@52 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1932,10 +1932,10 @@ cpu53: cpu@53 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1968,10 +1968,10 @@ cpu54: cpu@54 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2004,10 +2004,10 @@ cpu55: cpu@55 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2040,10 +2040,10 @@ cpu56: cpu@56 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2076,10 +2076,10 @@ cpu57: cpu@57 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2112,10 +2112,10 @@ cpu58: cpu@58 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2148,10 +2148,10 @@ cpu59: cpu@59 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2184,10 +2184,10 @@ cpu60: cpu@60 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2220,10 +2220,10 @@ cpu61: cpu@61 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2256,10 +2256,10 @@ cpu62: cpu@62 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2292,10 +2292,10 @@ cpu63: cpu@63 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", -- 2.43.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 3/4] riscv: dts: sophgo: sg2044: Add "b" ISA extension 2026-01-14 23:18 ` [PATCH v2 3/4] riscv: dts: sophgo: sg2044: " Guodong Xu @ 2026-01-15 0:28 ` Inochi Amaoto 0 siblings, 0 replies; 14+ messages in thread From: Inochi Amaoto @ 2026-01-15 0:28 UTC (permalink / raw) To: Guodong Xu, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Chen Wang, Inochi Amaoto, Yixun Lan, Conor Dooley Cc: Junhui Liu, linux-doc, linux-riscv, linux-kernel, devicetree, sophgo, spacemit On Thu, Jan 15, 2026 at 07:18:59AM +0800, Guodong Xu wrote: > "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs > (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency > checking rule is now enforced, which requires that when zba, zbb, and zbs > are all specified, "b" must be added as well. Failing to do this will > cause dtbs_check schema check warnings. > > According to uabi.rst, as a single-letter extension, "b" should be added > after "c" in canonical order. > > Update sg2044-cpus.dtsi to conform to this rule. > > Signed-off-by: Guodong Xu <guodong@riscstar.com> > --- > v2: New patch, a split from the Patch 2 in v1. This patch is for > Sophgo sg2044. > --- > arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 256 ++++++++++++++-------------- > 1 file changed, 128 insertions(+), 128 deletions(-) > LGTM, I will queue this patch for the next rc. Reviewed-by: Inochi Amaoto <inochiama@gmail.com> > diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi > index 523799a1a8b8..3135409c2149 100644 > --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi > +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi > @@ -24,10 +24,10 @@ cpu0: cpu@0 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache0>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -60,10 +60,10 @@ cpu1: cpu@1 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache0>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -96,10 +96,10 @@ cpu2: cpu@2 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache0>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -132,10 +132,10 @@ cpu3: cpu@3 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache0>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -168,10 +168,10 @@ cpu4: cpu@4 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache1>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -204,10 +204,10 @@ cpu5: cpu@5 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache1>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -240,10 +240,10 @@ cpu6: cpu@6 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache1>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -276,10 +276,10 @@ cpu7: cpu@7 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache1>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -312,10 +312,10 @@ cpu8: cpu@8 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache2>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -348,10 +348,10 @@ cpu9: cpu@9 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache2>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -384,10 +384,10 @@ cpu10: cpu@10 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache2>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -420,10 +420,10 @@ cpu11: cpu@11 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache2>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -456,10 +456,10 @@ cpu12: cpu@12 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache3>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -492,10 +492,10 @@ cpu13: cpu@13 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache3>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -528,10 +528,10 @@ cpu14: cpu@14 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache3>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -564,10 +564,10 @@ cpu15: cpu@15 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache3>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -600,10 +600,10 @@ cpu16: cpu@16 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache4>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -636,10 +636,10 @@ cpu17: cpu@17 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache4>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -672,10 +672,10 @@ cpu18: cpu@18 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache4>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -708,10 +708,10 @@ cpu19: cpu@19 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache4>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -744,10 +744,10 @@ cpu20: cpu@20 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache5>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -780,10 +780,10 @@ cpu21: cpu@21 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache5>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -816,10 +816,10 @@ cpu22: cpu@22 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache5>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -852,10 +852,10 @@ cpu23: cpu@23 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache5>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -888,10 +888,10 @@ cpu24: cpu@24 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache6>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -924,10 +924,10 @@ cpu25: cpu@25 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache6>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -960,10 +960,10 @@ cpu26: cpu@26 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache6>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -996,10 +996,10 @@ cpu27: cpu@27 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache6>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1032,10 +1032,10 @@ cpu28: cpu@28 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache7>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1068,10 +1068,10 @@ cpu29: cpu@29 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache7>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1104,10 +1104,10 @@ cpu30: cpu@30 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache7>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1140,10 +1140,10 @@ cpu31: cpu@31 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache7>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1176,10 +1176,10 @@ cpu32: cpu@32 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache8>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1212,10 +1212,10 @@ cpu33: cpu@33 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache8>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1248,10 +1248,10 @@ cpu34: cpu@34 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache8>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1284,10 +1284,10 @@ cpu35: cpu@35 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache8>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1320,10 +1320,10 @@ cpu36: cpu@36 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache9>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1356,10 +1356,10 @@ cpu37: cpu@37 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache9>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1392,10 +1392,10 @@ cpu38: cpu@38 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache9>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1428,10 +1428,10 @@ cpu39: cpu@39 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache9>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1464,10 +1464,10 @@ cpu40: cpu@40 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache10>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1500,10 +1500,10 @@ cpu41: cpu@41 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache10>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1536,10 +1536,10 @@ cpu42: cpu@42 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache10>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1572,10 +1572,10 @@ cpu43: cpu@43 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache10>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1608,10 +1608,10 @@ cpu44: cpu@44 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache11>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1644,10 +1644,10 @@ cpu45: cpu@45 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache11>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1680,10 +1680,10 @@ cpu46: cpu@46 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache11>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1716,10 +1716,10 @@ cpu47: cpu@47 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache11>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1752,10 +1752,10 @@ cpu48: cpu@48 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache12>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1788,10 +1788,10 @@ cpu49: cpu@49 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache12>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1824,10 +1824,10 @@ cpu50: cpu@50 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache12>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1860,10 +1860,10 @@ cpu51: cpu@51 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache12>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1896,10 +1896,10 @@ cpu52: cpu@52 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache13>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1932,10 +1932,10 @@ cpu53: cpu@53 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache13>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -1968,10 +1968,10 @@ cpu54: cpu@54 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache13>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -2004,10 +2004,10 @@ cpu55: cpu@55 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache13>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -2040,10 +2040,10 @@ cpu56: cpu@56 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache14>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -2076,10 +2076,10 @@ cpu57: cpu@57 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache14>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -2112,10 +2112,10 @@ cpu58: cpu@58 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache14>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -2148,10 +2148,10 @@ cpu59: cpu@59 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache14>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -2184,10 +2184,10 @@ cpu60: cpu@60 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache15>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -2220,10 +2220,10 @@ cpu61: cpu@61 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache15>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -2256,10 +2256,10 @@ cpu62: cpu@62 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache15>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > @@ -2292,10 +2292,10 @@ cpu63: cpu@63 { > device_type = "cpu"; > mmu-type = "riscv,sv48"; > next-level-cache = <&l2_cache15>; > - riscv,isa = "rv64imafdcv"; > + riscv,isa = "rv64imafdcbv"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > - "v", "sscofpmf", "sstc", > + "b", "v", "sscofpmf", "sstc", > "svinval", "svnapot", "svpbmt", > "zawrs", "zba", "zbb", "zbc", > "zbs", "zca", "zcb", "zcd", > > -- > 2.43.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 4/4] riscv: dts: spacemit: k1: Add "b" ISA extension 2026-01-14 23:18 [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees Guodong Xu ` (2 preceding siblings ...) 2026-01-14 23:18 ` [PATCH v2 3/4] riscv: dts: sophgo: sg2044: " Guodong Xu @ 2026-01-14 23:19 ` Guodong Xu 2026-01-15 0:39 ` Yixun Lan 2026-01-15 11:24 ` (subset) [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees Yixun Lan ` (2 subsequent siblings) 6 siblings, 1 reply; 14+ messages in thread From: Guodong Xu @ 2026-01-14 23:19 UTC (permalink / raw) To: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Chen Wang, Inochi Amaoto, Yixun Lan, Conor Dooley Cc: Junhui Liu, linux-doc, linux-riscv, linux-kernel, devicetree, sophgo, spacemit, Guodong Xu "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update k1.dtsi to conform to this rule. Signed-off-by: Guodong Xu <guodong@riscstar.com> --- v2: New patch, a split from the Patch 2 in v1. This patch is for Spacemit K1. --- arch/riscv/boot/dts/spacemit/k1.dtsi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 4c045da95d72..2917b315728f 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -54,9 +54,9 @@ cpu_0: cpu@0 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <0>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -84,9 +84,9 @@ cpu_1: cpu@1 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <1>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -114,9 +114,9 @@ cpu_2: cpu@2 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <2>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -144,9 +144,9 @@ cpu_3: cpu@3 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <3>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -174,9 +174,9 @@ cpu_4: cpu@4 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <4>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -204,9 +204,9 @@ cpu_5: cpu@5 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <5>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -234,9 +234,9 @@ cpu_6: cpu@6 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <6>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -264,9 +264,9 @@ cpu_7: cpu@7 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <7>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", -- 2.43.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 4/4] riscv: dts: spacemit: k1: Add "b" ISA extension 2026-01-14 23:19 ` [PATCH v2 4/4] riscv: dts: spacemit: k1: " Guodong Xu @ 2026-01-15 0:39 ` Yixun Lan 0 siblings, 0 replies; 14+ messages in thread From: Yixun Lan @ 2026-01-15 0:39 UTC (permalink / raw) To: Guodong Xu Cc: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Chen Wang, Inochi Amaoto, Conor Dooley, Junhui Liu, linux-doc, linux-riscv, linux-kernel, devicetree, sophgo, spacemit Hi Guodong, On 07:19 Thu 15 Jan , Guodong Xu wrote: > "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs > (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency > checking rule is now enforced, which requires that when zba, zbb, and zbs > are all specified, "b" must be added as well. Failing to do this will > cause dtbs_check schema check warnings. > > According to uabi.rst, as a single-letter extension, "b" should be added > after "c" in canonical order. > > Update k1.dtsi to conform to this rule. > > Signed-off-by: Guodong Xu <guodong@riscstar.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> -- Yixun Lan (dlan) ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: (subset) [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees 2026-01-14 23:18 [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees Guodong Xu ` (3 preceding siblings ...) 2026-01-14 23:19 ` [PATCH v2 4/4] riscv: dts: spacemit: k1: " Guodong Xu @ 2026-01-15 11:24 ` Yixun Lan 2026-01-15 19:13 ` Conor Dooley 2026-01-20 1:16 ` (subset) " Inochi Amaoto 6 siblings, 0 replies; 14+ messages in thread From: Yixun Lan @ 2026-01-15 11:24 UTC (permalink / raw) To: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Chen Wang, Inochi Amaoto, Yixun Lan, Conor Dooley, Guodong Xu Cc: Yixun Lan, Junhui Liu, linux-doc, linux-riscv, linux-kernel, devicetree, sophgo, spacemit On Thu, 15 Jan 2026 07:18:56 +0800, Guodong Xu wrote: > The RISC-V "b" (Bit-manipulation) extension was ratified in April 2024, > much later than its component extensions zba/zbb/zbs (June 2021). Recent > updates to the device tree bindings [2] enforce that when all three > component extensions are present, "b" must also be specified. Related > discussion can also be found in [1]. > > Patch 1 clarifies the ISA spec version for canonical ordering in uabi.rst. > It is a trivial update, but can help readers reference the correct > document version. Acked-by Paul Walmsley in v1. > > [...] Applied, thanks! [4/4] riscv: dts: spacemit: k1: Add "b" ISA extension https://github.com/spacemit-com/linux/commit/eb241eb29bad28cd17c5a4b9c355645e96094713 Best regards, -- Yixun Lan <dlan@kernel.org> ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees 2026-01-14 23:18 [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees Guodong Xu ` (4 preceding siblings ...) 2026-01-15 11:24 ` (subset) [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees Yixun Lan @ 2026-01-15 19:13 ` Conor Dooley 2026-01-15 23:04 ` Guodong Xu 2026-01-20 1:16 ` (subset) " Inochi Amaoto 6 siblings, 1 reply; 14+ messages in thread From: Conor Dooley @ 2026-01-15 19:13 UTC (permalink / raw) To: Guodong Xu Cc: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Chen Wang, Inochi Amaoto, Yixun Lan, Conor Dooley, Junhui Liu, linux-doc, linux-riscv, linux-kernel, devicetree, sophgo, spacemit [-- Attachment #1: Type: text/plain, Size: 3163 bytes --] On Thu, Jan 15, 2026 at 07:18:56AM +0800, Guodong Xu wrote: > The RISC-V "b" (Bit-manipulation) extension was ratified in April 2024, > much later than its component extensions zba/zbb/zbs (June 2021). Recent > updates to the device tree bindings [2] enforce that when all three > component extensions are present, "b" must also be specified. Related > discussion can also be found in [1]. > > Patch 1 clarifies the ISA spec version for canonical ordering in uabi.rst. > It is a trivial update, but can help readers reference the correct > document version. Acked-by Paul Walmsley in v1. > > Patch 2, 3 and 4 adds "b" after "c" in 3 different device tree files > respectivly, anlogic, sophgo and spacemit, fixing the related dtbs_check > warnings. > > This patchset is based on top of linux-next, tag: next-20260109, and > depends on [2]. > > Link: https://lore.kernel.org/all/20251230-imprison-sleet-6b5a1e26d34b@spud/ [1] > Link: https://lore.kernel.org/all/20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com/ [2] > > Changes in v2: > - Patch 1: Add Acked-by from Paul Walmsley. > - Patch 2/3/4: These are splits from the v1 Patch 2. Split into three > different patches for each SoC. > - Link to v1: https://lore.kernel.org/r/20260113-adding-b-dtsi-v1-0-22d6e55d19df@riscstar.com > > Signed-off-by: Guodong Xu <guodong@riscstar.com> > --- > Guodong Xu (4): > Documentation: riscv: uabi: Clarify ISA spec version for canonical order > riscv: dts: anlogic: dr1v90: Add "b" ISA extension > riscv: dts: sophgo: sg2044: Add "b" ISA extension > riscv: dts: spacemit: k1: Add "b" ISA extension > > Documentation/arch/riscv/uabi.rst | 4 +- > arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 5 +- > arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 256 ++++++++++++++-------------- > arch/riscv/boot/dts/spacemit/k1.dtsi | 32 ++-- > 4 files changed, 150 insertions(+), 147 deletions(-) > --- > base-commit: 31d167f54de93f14fa8e4bc6cbc4adaf7019fd94 > change-id: 20260113-adding-b-dtsi-148714533f07 > prerequisite-message-id: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> > prerequisite-patch-id: 0c859b4d131b3360875c795c6148c6176b55fb91 > prerequisite-patch-id: 2ed98dc1ab0f5ed923cc252415c345dc8caf6f17 > prerequisite-patch-id: 1be1a031763fac029076a768f012af31e455be66 > prerequisite-patch-id: 21bb8387c946e050910440e7a7622305d46d946d > prerequisite-patch-id: f3bdc2c74b230663710086bd770a755d56cb8b9c > prerequisite-patch-id: 1f162c02f8bdb5bbc8ce52ead4fcb76258f5c2b9 > prerequisite-patch-id: 76e1ff26c2f1fe4019cfa574942b568000e6ca1f > prerequisite-patch-id: 77ddc9e5dc85495adc803cdc605bdda2ddc7fa47 > prerequisite-patch-id: a75c798383b46a14d40436357c769c3671184768 > prerequisite-patch-id: 781fc10dcae2c38c84c25bee887ef7474786dd36 > prerequisite-patch-id: 5be5d3e62aa73024bf9e1de6aad155be6d618f40 FWIW, this kind of prereq-patch-id stuff isn't really helpful, because I don't think there's actually any dependencies on that work. It actually trips up some parts of b4 that think they're needed. I applied the Anlogic patch. Thanks, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees 2026-01-15 19:13 ` Conor Dooley @ 2026-01-15 23:04 ` Guodong Xu 0 siblings, 0 replies; 14+ messages in thread From: Guodong Xu @ 2026-01-15 23:04 UTC (permalink / raw) To: Conor Dooley Cc: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Chen Wang, Inochi Amaoto, Yixun Lan, Conor Dooley, Junhui Liu, linux-doc, linux-riscv, linux-kernel, devicetree, sophgo, spacemit On Fri, Jan 16, 2026 at 3:13 AM Conor Dooley <conor@kernel.org> wrote: > > On Thu, Jan 15, 2026 at 07:18:56AM +0800, Guodong Xu wrote: > > --- > > base-commit: 31d167f54de93f14fa8e4bc6cbc4adaf7019fd94 > > change-id: 20260113-adding-b-dtsi-148714533f07 > > prerequisite-message-id: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> > > prerequisite-patch-id: 0c859b4d131b3360875c795c6148c6176b55fb91 > > prerequisite-patch-id: 2ed98dc1ab0f5ed923cc252415c345dc8caf6f17 > > prerequisite-patch-id: 1be1a031763fac029076a768f012af31e455be66 > > prerequisite-patch-id: 21bb8387c946e050910440e7a7622305d46d946d > > prerequisite-patch-id: f3bdc2c74b230663710086bd770a755d56cb8b9c > > prerequisite-patch-id: 1f162c02f8bdb5bbc8ce52ead4fcb76258f5c2b9 > > prerequisite-patch-id: 76e1ff26c2f1fe4019cfa574942b568000e6ca1f > > prerequisite-patch-id: 77ddc9e5dc85495adc803cdc605bdda2ddc7fa47 > > prerequisite-patch-id: a75c798383b46a14d40436357c769c3671184768 > > prerequisite-patch-id: 781fc10dcae2c38c84c25bee887ef7474786dd36 > > prerequisite-patch-id: 5be5d3e62aa73024bf9e1de6aad155be6d618f40 > > FWIW, this kind of prereq-patch-id stuff isn't really helpful, because I > don't think there's actually any dependencies on that work. It actually > trips up some parts of b4 that think they're needed. Noted. Using individual patch message-ids is better in a case like this. Above, I put the entire series' message-id, which creates unrelated prerequisite stuff, as you pointed out. > > I applied the Anlogic patch. Thanks Conor. BR, Guodong Xu > > Thanks, > Conor. ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: (subset) [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees 2026-01-14 23:18 [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees Guodong Xu ` (5 preceding siblings ...) 2026-01-15 19:13 ` Conor Dooley @ 2026-01-20 1:16 ` Inochi Amaoto 2026-01-20 2:48 ` Inochi Amaoto 6 siblings, 1 reply; 14+ messages in thread From: Inochi Amaoto @ 2026-01-20 1:16 UTC (permalink / raw) To: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Chen Wang, Yixun Lan, Conor Dooley, Guodong Xu Cc: Inochi Amaoto, Junhui Liu, linux-doc, linux-riscv, linux-kernel, devicetree, sophgo, spacemit On Thu, 15 Jan 2026 07:18:56 +0800, Guodong Xu wrote: > The RISC-V "b" (Bit-manipulation) extension was ratified in April 2024, > much later than its component extensions zba/zbb/zbs (June 2021). Recent > updates to the device tree bindings [2] enforce that when all three > component extensions are present, "b" must also be specified. Related > discussion can also be found in [1]. > > Patch 1 clarifies the ISA spec version for canonical ordering in uabi.rst. > It is a trivial update, but can help readers reference the correct > document version. Acked-by Paul Walmsley in v1. > > [...] Applied to dt/riscv, thanks! [3/4] riscv: dts: sophgo: sg2044: Add "b" ISA extension https://github.com/sophgo/linux/commit/f16ae81b80ca4e721f4c4ed1f28390115f7721eb Thanks, Inochi ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: (subset) [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees 2026-01-20 1:16 ` (subset) " Inochi Amaoto @ 2026-01-20 2:48 ` Inochi Amaoto 0 siblings, 0 replies; 14+ messages in thread From: Inochi Amaoto @ 2026-01-20 2:48 UTC (permalink / raw) To: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Conor Dooley, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Chen Wang, Yixun Lan, Conor Dooley, Guodong Xu Cc: Inochi Amaoto, Junhui Liu, linux-doc, linux-riscv, linux-kernel, devicetree, sophgo, spacemit On Thu, 15 Jan 2026 07:18:56 +0800, Guodong Xu wrote: > The RISC-V "b" (Bit-manipulation) extension was ratified in April 2024, > much later than its component extensions zba/zbb/zbs (June 2021). Recent > updates to the device tree bindings [2] enforce that when all three > component extensions are present, "b" must also be specified. Related > discussion can also be found in [1]. > > Patch 1 clarifies the ISA spec version for canonical ordering in uabi.rst. > It is a trivial update, but can help readers reference the correct > document version. Acked-by Paul Walmsley in v1. > > [...] Applied to dt/riscv, thanks! [3/4] riscv: dts: sophgo: sg2044: Add "b" ISA extension https://github.com/sophgo/linux/commit/f16ae81b80ca4e721f4c4ed1f28390115f7721eb Thanks, Inochi ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2026-01-20 4:47 UTC | newest] Thread overview: 14+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-01-14 23:18 [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees Guodong Xu 2026-01-14 23:18 ` [PATCH v2 1/4] Documentation: riscv: uabi: Clarify ISA spec version for canonical order Guodong Xu 2026-01-15 0:10 ` Paul Walmsley 2026-01-14 23:18 ` [PATCH v2 2/4] riscv: dts: anlogic: dr1v90: Add "b" ISA extension Guodong Xu 2026-01-15 2:25 ` Junhui Liu 2026-01-14 23:18 ` [PATCH v2 3/4] riscv: dts: sophgo: sg2044: " Guodong Xu 2026-01-15 0:28 ` Inochi Amaoto 2026-01-14 23:19 ` [PATCH v2 4/4] riscv: dts: spacemit: k1: " Guodong Xu 2026-01-15 0:39 ` Yixun Lan 2026-01-15 11:24 ` (subset) [PATCH v2 0/4] riscv: dts: Add "b" ISA extension to existing devicetrees Yixun Lan 2026-01-15 19:13 ` Conor Dooley 2026-01-15 23:04 ` Guodong Xu 2026-01-20 1:16 ` (subset) " Inochi Amaoto 2026-01-20 2:48 ` Inochi Amaoto
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