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[142.162.112.119]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cda1fddfe8sm328304485a.12.2026.03.12.05.26.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 05:26:46 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1w0f7l-00000006ewH-1owB; Thu, 12 Mar 2026 09:26:45 -0300 Date: Thu, 12 Mar 2026 09:26:45 -0300 From: Jason Gunthorpe To: Leon Romanovsky Cc: Marek Szyprowski , Robin Murphy , "Michael S. Tsirkin" , Petr Tesarik , Jonathan Corbet , Shuah Khan , Jason Wang , Xuan Zhuo , Eugenio =?utf-8?B?UMOpcmV6?= , Steven Rostedt , Masami Hiramatsu , Mathieu Desnoyers , Joerg Roedel , Will Deacon , Andrew Morton , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, virtualization@lists.linux.dev, linux-rdma@vger.kernel.org, linux-trace-kernel@vger.kernel.org, linux-mm@kvack.org Subject: Re: [PATCH v2 8/8] mm/hmm: Indicate that HMM requires DMA coherency Message-ID: <20260312122645.GG1469476@ziepe.ca> References: <20260311-dma-debug-overlap-v2-0-e00bc2ca346d@nvidia.com> <20260311-dma-debug-overlap-v2-8-e00bc2ca346d@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260311-dma-debug-overlap-v2-8-e00bc2ca346d@nvidia.com> On Wed, Mar 11, 2026 at 09:08:51PM +0200, Leon Romanovsky wrote: > From: Leon Romanovsky > > HMM mirroring can work on coherent systems without SWIOTLB path only. > Until introduction of DMA_ATTR_REQUIRE_COHERENT, there was no reliable > way to indicate that and various approximation was done: HMM is fundamentally about allowing a sophisticated device to independently DMA to a process's memory concurrently with the CPU accessing the same memory. It is similar to SVA but does not rely on IOMMU support. Since the entire use model is concurrent access to the same memory it becomes fatally broken as a uAPI if SWIOTLB is replacing the memory, or the CPU caches are incoherent with DMA. Till now there was no reliable way to indicate that and various approximation was done: > int hmm_dma_map_alloc(struct device *dev, struct hmm_dma_map *map, > size_t nr_entries, size_t dma_entry_size) > { > <...> > /* > * The HMM API violates our normal DMA buffer ownership rules and can't > * transfer buffer ownership. The dma_addressing_limited() check is a > * best approximation to ensure no swiotlb buffering happens. > */ > dma_need_sync = !dev->dma_skip_sync; > if (dma_need_sync || dma_addressing_limited(dev)) > return -EOPNOTSUPP; Can it get dropped now then? > So let's mark mapped buffers with DMA_ATTR_REQUIRE_COHERENT attribute > to prevent DMA debugging warnings for cache overlapped entries. Well, that isn't the main motivation, this prevents silent data corruption if someone tries to use hmm in a system with swiotlb or incoherent DMA, Looks OK otherwise Reviewed-by: Jason Gunthorpe Jason