From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5135839150B; Tue, 7 Apr 2026 17:52:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775584351; cv=none; b=u49Dno5e4HNa/CdVGWDXkNIlLD/MamlrF6gRRONBgJ/oMx+zJ954I2JAckSpJhc3t4ox0wSmBVBTyGVxwHc5Jk+oStkarTeGyrZ5kymGcuivK+6pp2C6E60wykMvmvNITGf6tyAA34DhrGIh00pIdiqjrkU39i456FDgS7DPjIg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775584351; c=relaxed/simple; bh=3fkEJFFrgqy6MjrcRSqfdHOdo4sUYO6cXLb/hD4bbJE=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=rrKKhq6liAke1NdTqKdOvlJ3hlU8OEZXMW9I0PRZqw0W08zo5MqVCdct7foQF+wQsFW2LhExAU5NQE05uH/K6X048K29rQmUjw7pFZLcJh/tanLuw1n+R0qjo/wQh+5Nz8mJlsMV5v7Yos6UoQYXpFKK2CrHHi4hrZLx82WCLH0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZfZGZ9RS; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZfZGZ9RS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1775584348; x=1807120348; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=3fkEJFFrgqy6MjrcRSqfdHOdo4sUYO6cXLb/hD4bbJE=; b=ZfZGZ9RSVVUWvofDn0gKvRDaUUQ8GNjaIIP+Zv/nDR14Rp8EA7BnvcLh oCEMm0jdMyheZm4oJhI+taByO5ZCylCTMp0YhELOIuGjmwzY7mxTPb5fw tm0wkBCDzj2S34Yshe1ZbkVdl9I9U5+lbzw0H5B7FY3/S7tyqjH3WEygq K1S4Ivmk1TWnnNbdpupzH8VdfW96pq3iV6wGPbMr3RGLdK253Xl4qEl+Q gRdRzr2B0ri7iGHO8fFgQJcZ9Q/m1lHPxllxBzTFbRT6Ig2EqI976ASXO MHImjAhdngG+O/BVuGNlrG7765s9FerPCrr0o/tSDkuzUM7q0dQFcHK/b w==; X-CSE-ConnectionGUID: e+snA+APRoiD1jp68msHpA== X-CSE-MsgGUID: tW/ZJIB+Tn6tD/tnnr0IGw== X-IronPort-AV: E=McAfee;i="6800,10657,11752"; a="86849748" X-IronPort-AV: E=Sophos;i="6.23,166,1770624000"; d="scan'208";a="86849748" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2026 10:52:27 -0700 X-CSE-ConnectionGUID: U0nsAuVHTcSOdZVcP9udKA== X-CSE-MsgGUID: pG8Pe/rGRBK4wc6fe0pTxg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,166,1770624000"; d="scan'208";a="233114723" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2026 10:52:23 -0700 Date: Tue, 7 Apr 2026 10:52:07 -0700 From: Pawan Gupta To: Jon Kohler Cc: Jim Mattson , "x86@kernel.org" , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , Asit Mallick , Tao Zhang , "bpf@vger.kernel.org" , "netdev@vger.kernel.org" , "linux-doc@vger.kernel.org" , "chao.gao@intel.com" Subject: Re: [PATCH v9 02/10] x86/bhi: Make clear_bhb_loop() effective on newer CPUs Message-ID: <20260407175207.j5atzf772mkdezgg@desk> References: <20260403233329.fb2ppifgwm3um6ny@desk> <20260404002149.wtayv6a64vzuppgp@desk> <20260404034954.t7iapenzvhdpagxp@desk> <20260407163943.y6tkh26z2rfktn3y@desk> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Tue, Apr 07, 2026 at 05:12:06PM +0000, Jon Kohler wrote: > > > > On Apr 7, 2026, at 11:46 AM, Jim Mattson wrote: > > > > On Tue, Apr 7, 2026 at 9:40 AM Pawan Gupta > > wrote: > >> > >> On Mon, Apr 06, 2026 at 07:23:25AM -0700, Jim Mattson wrote: > >>> Yes, but the guest needs a way to determine whether the hypervisor > >>> will do what's necessary to make the short sequence effective. And, in > >>> particular, no KVM hypervisor today is prepared to do that. > >>> > >>> When running under a hypervisor, without BHI_CTRL and without any > >>> evidence to the contrary, the guest must assume that the longer > >>> sequence is necessary. At the very least, we need a CPUID or MSR bit > >>> that says, "the short BHB clearing sequence is adequate for this > >>> vCPU." > >> > >> After discussing this internally, the consensus is that the best path > >> forward is to add virtual SPEC_CTRL support to KVM, which also aligns with > >> Intel's guidance. In the long term, virtual SPEC_CTRL can benefit future > >> mitigations as well. As with many other mitigations (e.g. microcode), the > >> guest would rely on the host to enforce the appropriate protections. > > Would we have to wait for virtual SPEC_CTRL to get this optimization? The optimization works with or without virtual-SPEC_CTRL. > Or would that be a future enhancement to make this more prescriptive? Virtual-SPEC_CTRL enables safer guest migrations between pre and post Alder Lake CPUs w.r.t. Native BHI mitigation. It is not related to VMSCAPE.