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b=hrkWhH6j6dbDktUwtoim03erfrwb6EhnCqWA6ZHZxitFsuDhI2aoJg1c1sj69IyvQB8q7rUdDmrRjidy9dq5gnHg1bzpgLmiQv5Sp4hQ1iBuIf3DaSYHyymrTXEJDefIb0GZV1cH8rwT0Sx5Yxgxu1s6Q4OjGfknekVj+3AGZvfLGdqjKqDgXU77xWWMDjiCabUeI419+2zk1hkANfaEaQQA41lA0ed30GYoKFkB4ArakUAmSIM4qYKWl1LWbBbTju02o+DqYHwbxSIOzH4QgxASkwH+lGq3ctvuA6aZlPt+u9DKtLz/752HtE4KWhgqOVt6IcRvTGwJxLVF/jH3og== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by IA1PR12MB8358.namprd12.prod.outlook.com (2603:10b6:208:3fa::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9870.13; Sat, 25 Apr 2026 21:15:17 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9870.012; Sat, 25 Apr 2026 21:15:17 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Miguel Ojeda , Boqun Feng , Gary Guo , Bjorn Roy Baron , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Dave Airlie , Daniel Almeida , dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, nova-gpu@lists.linux.dev, Nikola Djukic , David Airlie , Boqun Feng , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Balbir Singh , Philipp Stanner , alexeyi@nvidia.com, Eliot Courtney , joel@joelfernandes.org, linux-doc@vger.kernel.org, Joel Fernandes Subject: [PATCH v12 04/22] gpu: nova-core: mm: Add support to use PRAMIN windows to write to VRAM Date: Sat, 25 Apr 2026 17:14:36 -0400 Message-Id: <20260425211454.174696-5-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260425211454.174696-1-joelagnelf@nvidia.com> References: <20260425211454.174696-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: BL1PR13CA0250.namprd13.prod.outlook.com (2603:10b6:208:2ba::15) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|IA1PR12MB8358:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f7abfe1-377a-428a-7bc4-08dea30fbfa8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|56012099003|18002099003|22082099003|11006099003; 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Add support for the same. Cc: Nikola Djukic Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm.rs | 5 + drivers/gpu/nova-core/mm/pramin.rs | 300 +++++++++++++++++++++++++++++ drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/regs.rs | 10 + 4 files changed, 316 insertions(+) create mode 100644 drivers/gpu/nova-core/mm.rs create mode 100644 drivers/gpu/nova-core/mm/pramin.rs diff --git a/drivers/gpu/nova-core/mm.rs b/drivers/gpu/nova-core/mm.rs new file mode 100644 index 000000000000..7a5dd4220c67 --- /dev/null +++ b/drivers/gpu/nova-core/mm.rs @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Memory management subsystems for nova-core. + +pub(crate) mod pramin; diff --git a/drivers/gpu/nova-core/mm/pramin.rs b/drivers/gpu/nova-core/mm/pramin.rs new file mode 100644 index 000000000000..57b560ae1e85 --- /dev/null +++ b/drivers/gpu/nova-core/mm/pramin.rs @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Direct VRAM access through the PRAMIN aperture. +//! +//! PRAMIN provides a 1MB sliding window into VRAM through BAR0, allowing the CPU to access +//! video memory directly. Access is managed through a two-level API: +//! +//! - [`Pramin`]: The parent object that owns the BAR0 reference and synchronization lock. +//! - [`PraminWindow`]: A guard object that holds exclusive PRAMIN access for its lifetime. +//! +//! The PRAMIN aperture is a 1MB region at a fixed offset from BAR0. The window base is +//! controlled by an architecture-specific register and is 64KB aligned. +//! +//! # Examples +//! +//! ## Basic read/write +//! +//! ```no_run +//! use crate::driver::Bar0; +//! use crate::gpu::Chipset; +//! use crate::mm::pramin; +//! use kernel::device; +//! use kernel::devres::Devres; +//! use kernel::prelude::*; +//! use kernel::sync::Arc; +//! +//! fn example( +//! devres_bar: Arc>, +//! dev: &device::Device, +//! chipset: Chipset, +//! vram_region: core::ops::Range, +//! ) -> Result<()> { +//! let pramin = Arc::pin_init( +//! pramin::Pramin::new(devres_bar, dev, chipset, vram_region)?, +//! GFP_KERNEL, +//! )?; +//! let mut window = pramin.get_window(dev)?; +//! +//! // Write and read back. +//! window.try_write32(0x100, 0xDEADBEEF)?; +//! let val = window.try_read32(0x100)?; +//! assert_eq!(val, 0xDEADBEEF); +//! +//! Ok(()) +//! } +//! ``` +//! +//! ## Auto-repositioning across VRAM regions +//! +//! ```no_run +//! use crate::driver::Bar0; +//! use crate::gpu::Chipset; +//! use crate::mm::pramin; +//! use kernel::device; +//! use kernel::devres::Devres; +//! use kernel::prelude::*; +//! use kernel::sync::Arc; +//! +//! fn example( +//! devres_bar: Arc>, +//! dev: &device::Device, +//! chipset: Chipset, +//! vram_region: core::ops::Range, +//! ) -> Result<()> { +//! let pramin = Arc::pin_init( +//! pramin::Pramin::new(devres_bar, dev, chipset, vram_region)?, +//! GFP_KERNEL, +//! )?; +//! let mut window = pramin.get_window(dev)?; +//! +//! // Access first 1MB region. +//! window.try_write32(0x100, 0x11111111)?; +//! +//! // Access at 2MB - window auto-repositions. +//! window.try_write32(0x200000, 0x22222222)?; +//! +//! // Back to first region - window repositions again. +//! let val = window.try_read32(0x100)?; +//! assert_eq!(val, 0x11111111); +//! +//! Ok(()) +//! } +//! ``` + +#![expect(unused)] + +use core::ops::Range; + +use crate::{ + bounded_enum, + driver::Bar0, + num::IntoSafeCast, + regs, // +}; + +use kernel::{ + devres::Devres, + io::Io, + new_mutex, + num::Bounded, + prelude::*, + revocable::RevocableGuard, + sizes::{ + SZ_1M, + SZ_64K, // + }, + sync::{ + lock::mutex::MutexGuard, + Arc, + Mutex, // + }, +}; + +bounded_enum! { + /// Target memory type for the BAR0 window register. + /// + /// Only VRAM is supported; Hopper+ GPUs do not support other targets. + #[derive(Debug)] + pub(crate) enum Bar0WindowTarget with TryFrom> { + /// Video RAM (GPU framebuffer memory). + Vram = 0, + } +} + +/// PRAMIN aperture base offset in BAR0. +const PRAMIN_BASE: usize = 0x700000; + +/// PRAMIN aperture size (1MB). +const PRAMIN_SIZE: usize = SZ_1M; + +/// Generate a PRAMIN read accessor. +macro_rules! define_pramin_read { + ($name:ident, $ty:ty) => { + #[doc = concat!("Read a `", stringify!($ty), "` from VRAM at the given offset.")] + pub(crate) fn $name(&mut self, vram_offset: usize) -> Result<$ty> { + let (bar_offset, new_base) = + self.compute_window(vram_offset, ::core::mem::size_of::<$ty>())?; + + if let Some(base) = new_base { + Self::write_window_base(&self.bar, base)?; + *self.state = base; + } + self.bar.$name(bar_offset) + } + }; +} + +/// Generate a PRAMIN write accessor. +macro_rules! define_pramin_write { + ($name:ident, $ty:ty) => { + #[doc = concat!("Write a `", stringify!($ty), "` to VRAM at the given offset.")] + pub(crate) fn $name(&mut self, vram_offset: usize, value: $ty) -> Result { + let (bar_offset, new_base) = + self.compute_window(vram_offset, ::core::mem::size_of::<$ty>())?; + + if let Some(base) = new_base { + Self::write_window_base(&self.bar, base)?; + *self.state = base; + } + self.bar.$name(value, bar_offset) + } + }; +} + +/// PRAMIN aperture manager. +/// +/// Call [`Pramin::get_window()`] to acquire exclusive PRAMIN access. +#[pin_data] +pub(crate) struct Pramin { + bar: Arc>, + /// Valid VRAM region. Accesses outside this range are rejected. + vram_region: Range, + /// PRAMIN aperture state, protected by a mutex. + /// + /// # Invariants + /// + /// This lock is acquired during the DMA fence signaling critical path. + /// It must NEVER be held across any reclaimable CPU memory / allocations + /// (`GFP_KERNEL`), because the memory reclaim path can call + /// `dma_fence_wait()`, which would deadlock with this lock held. + #[pin] + state: Mutex, +} + +impl Pramin { + /// Create a pin-initializer for PRAMIN. + /// + /// `vram_region` specifies the valid VRAM address range. + pub(crate) fn new( + bar: Arc>, + vram_region: Range, + ) -> Result> { + let bar_access = bar.try_access().ok_or(ENODEV)?; + let current_base = Self::read_window_base(&bar_access); + + Ok(pin_init!(Self { + bar, + vram_region, + state <- new_mutex!(current_base, "pramin_state"), + })) + } + + /// Acquire exclusive PRAMIN access. + /// + /// Returns a [`PraminWindow`] guard that provides VRAM read/write accessors. + /// The [`PraminWindow`] is exclusive and only one can exist at a time. + pub(crate) fn get_window(&self) -> Result> { + let bar = self.bar.try_access().ok_or(ENODEV)?; + let state = self.state.lock(); + Ok(PraminWindow { + bar, + vram_region: self.vram_region.clone(), + state, + }) + } + + /// Read the current window base from the BAR0_WINDOW register. + fn read_window_base(bar: &Bar0) -> u64 { + let reg = bar.read(regs::NV_PBUS_BAR0_WINDOW); + + // TODO: Convert to Bounded when available. + u64::from(reg.window_base()) << 16 + } +} + +/// PRAMIN window guard for direct VRAM access. +/// +/// This guard holds exclusive access to the PRAMIN aperture. The window auto-repositions +/// when accessing VRAM offsets outside the current 1MB range. +/// +/// Only one [`PraminWindow`] can exist at a time per [`Pramin`] instance (enforced by the +/// internal `MutexGuard`). +pub(crate) struct PraminWindow<'a> { + bar: RevocableGuard<'a, Bar0>, + vram_region: Range, + state: MutexGuard<'a, u64>, +} + +impl PraminWindow<'_> { + /// Write a new window base to the BAR0_WINDOW register. + fn write_window_base(bar: &Bar0, base: u64) -> Result { + // CAST: After >> 16, a VRAM address fits in u32. + let window_base = (base >> 16) as u32; + bar.write_reg( + regs::NV_PBUS_BAR0_WINDOW::zeroed() + .with_target(Bar0WindowTarget::Vram) + .try_with_window_base(window_base)?, + ); + Ok(()) + } + + /// Compute window parameters for a VRAM access. + /// + /// Returns (`bar_offset`, `new_base`) where: + /// - `bar_offset`: The BAR0 offset to use for the access. + /// - `new_base`: `Some(base)` if window needs repositioning, `None` otherwise. + fn compute_window( + &self, + vram_offset: usize, + access_size: usize, + ) -> Result<(usize, Option)> { + // Validate VRAM offset is within the valid VRAM region. + let vram_addr = vram_offset as u64; + let end_addr = vram_addr.checked_add(access_size as u64).ok_or(EINVAL)?; + if vram_addr < self.vram_region.start || end_addr > self.vram_region.end { + return Err(EINVAL); + } + + // Check if access fits within the current 1MB window. + let current_base = *self.state; + if vram_addr >= current_base { + let offset_in_window: usize = (vram_addr - current_base).into_safe_cast(); + if offset_in_window + access_size <= PRAMIN_SIZE { + return Ok((PRAMIN_BASE + offset_in_window, None)); + } + } + + // Access doesn't fit in current window - reposition. + // Hardware requires 64KB alignment for the window base register. + let needed_base = vram_addr & !(SZ_64K as u64 - 1); + let offset_in_window: usize = (vram_addr - needed_base).into_safe_cast(); + + // Verify access fits in the 1MB window from the new base. + if offset_in_window + access_size > PRAMIN_SIZE { + return Err(EINVAL); + } + + Ok((PRAMIN_BASE + offset_in_window, Some(needed_base))) + } + + define_pramin_read!(try_read8, u8); + define_pramin_read!(try_read16, u16); + define_pramin_read!(try_read32, u32); + define_pramin_read!(try_read64, u64); + + define_pramin_write!(try_write8, u8); + define_pramin_write!(try_write16, u16); + define_pramin_write!(try_write32, u32); + define_pramin_write!(try_write64, u64); +} diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nova_core.rs index 3a0c45481a92..d087354f03b9 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -17,6 +17,7 @@ mod gfw; mod gpu; mod gsp; +mod mm; #[macro_use] mod num; mod regs; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 2f171a4ff9ba..a3ca02345e20 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -30,6 +30,7 @@ Architecture, Chipset, // }, + mm::pramin::Bar0WindowTarget, num::FromSafeCast, }; @@ -115,6 +116,15 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> kernel::fmt::Result { } } +register! { + /// BAR0 window control for PRAMIN access. + pub(crate) NV_PBUS_BAR0_WINDOW(u32) @ 0x00001700 { + 25:24 target ?=> Bar0WindowTarget; + /// Window base address (bits 39:16 of FB addr). + 23:0 window_base; + } +} + // PFB register! { -- 2.34.1