From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ot1-f73.google.com (mail-ot1-f73.google.com [209.85.210.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9539B3EDAD6 for ; Mon, 4 May 2026 21:18:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.73 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777929525; cv=none; b=jQNdTO5tXOIWgglQvjXcjhCLj+0+asSMDllmHmlzX/ua1CBkXdU2zVBM0gFRItHCR7hGY3L3rwXGnysa0t/7SOSTi9JqPSnLUs3Sm1O8Q3yN8heYcY6IruUM7wW1dyPz3+i3M6ZrePOMA6QQRz/Kg5cx2RnjeHPDf2mWgbQYU+0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777929525; c=relaxed/simple; bh=Ju4hEvbWQIxue7C0GzlmuOc4hIQ+zS118FGwzfP52DY=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=tBCCr4mn3Zk7dpLlC2cwPR6Vy9biQjXadyTXir/88V+EM0tCI8DmyKupcu+Qeyj9SzxQEBq5F7sUaFfrX7VXFCPLnwRY45ZHyAXhNQ4FnVLAE1Fl1khDLfR604JW2ZBvrdiNVUWQ+KQKZzO18lhd1Mr5HIgE7kG/FOuPCXfaKTE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--coltonlewis.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=m21tjqFt; arc=none smtp.client-ip=209.85.210.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--coltonlewis.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="m21tjqFt" Received: by mail-ot1-f73.google.com with SMTP id 46e09a7af769-7dcda136050so7668731a34.2 for ; Mon, 04 May 2026 14:18:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1777929519; x=1778534319; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=2uXhxMRnzPluCmaQoLE1tgsrLMP2Ws4KNKFg4hBQdkY=; b=m21tjqFtASnNVjvZiZ1EiD4gwYhBnmuwpOax7H+OWTZaG5aZsk8yVTYCkMUkU38ikt B9eXHuULytkOwW+FGCwbU3ico7IvsLtsksdxl8otMmeMfzGcW3O/VLOY4Ud098jdTMli cwWzUT4SxhNbiyianVOMVQu6XeRZq4Ec+A4MneE+4HBNjh1Rdn9semlGPd4Kwy4ncOru aOFE5RVYHOz51iU5KRcVu3zcYW4dNYbmpLQijCHPX1hckE196iDRr2GVntxCvWEytXYJ F2m3M0fvKa9QRSLJMv6KTZzg6RUMQ+5RD+hU6EFQTrbgXzOnmsSgCw0/QNu3CvHF4hwj 0kGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777929519; x=1778534319; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=2uXhxMRnzPluCmaQoLE1tgsrLMP2Ws4KNKFg4hBQdkY=; b=L1r9cmWp66kfPV3mN6rmRG2ipFXiZm34qdAJTFbSKW7jilj0agGa2ElzPMSQXbFb+u Lo0X0jT9SLtHPn7p/X5IG6inhnI4/sjliXxbZJV+rhD6+2zSjmvlZeSlXFm/VArpEUbN /yeCmSvO3Z54YJuoOx+8yu7nUufPDqZMu89xSWi32H0/SsgoP/uMgO2YQVugu03XIz2l gX2XbP1UEt81Q8+wqC10H/fJErahVAQKMkle4mBveNMDweiqA7FXgzuCCUa6BrpMhSvD 0xjj0M5nwsN5gyIV0FyTTQ/VGMUBjbZ698LxpAuCYs4rCdn9ul4E1tU+eZItONYPHkJC pslQ== X-Forwarded-Encrypted: i=1; AFNElJ9w5X7bDK0/yo0Ih5yljFJ3NArlVErD871IGhSEbvLyMOLyBM8V9hUfl/qYnYPFQBS+BpRuR4K3P2o=@vger.kernel.org X-Gm-Message-State: AOJu0Yy9e7hrq7yg5cXS6XyiIyJokgxxMfCBuvjIMIakEg4dzlO29BXB wy5MHYA+YdjaRf2ft3b1l2PNth6/xYZqZdTf8RF4i9HhpAuLM4P9iRYh3VgjpwCLTPXBSm/7lgA /MKnzceJJKbgvOx1Et6AIlhiE7w== X-Received: from ilsi9.prod.google.com ([2002:a05:6e02:549:b0:4fe:73ca:fda6]) (user=coltonlewis job=prod-delivery.src-stubby-dispatcher) by 2002:a4a:e911:0:b0:684:188a:737d with SMTP id 006d021491bc7-6998d257e73mr177660eaf.44.1777929518793; Mon, 04 May 2026 14:18:38 -0700 (PDT) Date: Mon, 4 May 2026 21:18:02 +0000 In-Reply-To: <20260504211813.1804997-1-coltonlewis@google.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260504211813.1804997-1-coltonlewis@google.com> X-Mailer: git-send-email 2.54.0.545.g6539524ca2-goog Message-ID: <20260504211813.1804997-10-coltonlewis@google.com> Subject: [PATCH v7 09/20] KVM: arm64: Set up MDCR_EL2 to handle a Partitioned PMU From: Colton Lewis To: kvm@vger.kernel.org Cc: Alexandru Elisei , Paolo Bonzini , Jonathan Corbet , Russell King , Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Mingwei Zhang , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mark Rutland , Shuah Khan , Ganapatrao Kulkarni , James Clark , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, Colton Lewis Content-Type: text/plain; charset="UTF-8" Set up MDCR_EL2 to handle a Partitioned PMU. That means calculate an appropriate value for HPMN instead of the default maximum setting the host allows (which implies no partition) so hardware enforces that a guest will only see the counters in the guest partition. Setting HPMN to a non default value means the global enable bit for the host counters is now MDCR_EL2.HPME instead of the usual PMCR_EL0.E. Enable the HPME bit to allow the host to count guest events. Since HPME only has an effect when HPMN is set which we only do for the guest, it is correct to enable it unconditionally here. Unset the TPM and TPMCR bits, which trap all PMU accesses, if FGT (fine grain trapping) is being used. If available, set the filtering bits HPMD and HCCD to be extra sure nothing in the guest counts at EL2. Signed-off-by: Colton Lewis --- arch/arm64/kvm/debug.c | 29 ++++++++++++++++++++++++++--- arch/arm64/kvm/pmu-direct.c | 24 ++++++++++++++++++++++++ arch/arm64/kvm/pmu.c | 7 +++++++ include/kvm/arm_pmu.h | 11 +++++++++++ 4 files changed, 68 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index 3ad6b7c6e4ba7..0ab89c91e19cb 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -36,20 +36,43 @@ static int cpu_has_spe(u64 dfr0) */ static void kvm_arm_setup_mdcr_el2(struct kvm_vcpu *vcpu) { + int hpmn = kvm_pmu_hpmn(vcpu); + preempt_disable(); /* * This also clears MDCR_EL2_E2PB_MASK and MDCR_EL2_E2TB_MASK * to disable guest access to the profiling and trace buffers */ - vcpu->arch.mdcr_el2 = FIELD_PREP(MDCR_EL2_HPMN, - *host_data_ptr(nr_event_counters)); + + vcpu->arch.mdcr_el2 = FIELD_PREP(MDCR_EL2_HPMN, hpmn); vcpu->arch.mdcr_el2 |= (MDCR_EL2_TPM | MDCR_EL2_TPMS | MDCR_EL2_TTRF | MDCR_EL2_TPMCR | MDCR_EL2_TDRA | - MDCR_EL2_TDOSA); + MDCR_EL2_TDOSA | + MDCR_EL2_HPME); + + if (kvm_vcpu_pmu_is_partitioned(vcpu)) { + /* + * Filtering these should be redundant because we trap + * all the TYPER and FILTR registers anyway and ensure + * they filter EL2, but set the bits if they are here. + */ + if (is_pmuv3p1(read_pmuver())) + vcpu->arch.mdcr_el2 |= MDCR_EL2_HPMD; + if (is_pmuv3p5(read_pmuver())) + vcpu->arch.mdcr_el2 |= MDCR_EL2_HCCD; + + /* + * Take out the coarse grain traps if we are using + * fine grain traps. + */ + if (kvm_vcpu_pmu_use_fgt(vcpu)) + vcpu->arch.mdcr_el2 &= ~(MDCR_EL2_TPM | MDCR_EL2_TPMCR); + + } /* Is the VM being debugged by userspace? */ if (vcpu->guest_debug) diff --git a/arch/arm64/kvm/pmu-direct.c b/arch/arm64/kvm/pmu-direct.c index 2148bc46079c4..63ac72910e4b5 100644 --- a/arch/arm64/kvm/pmu-direct.c +++ b/arch/arm64/kvm/pmu-direct.c @@ -74,3 +74,27 @@ bool kvm_vcpu_pmu_use_fgt(struct kvm_vcpu *vcpu) cpus_have_final_cap(ARM64_HAS_FGT) && (hpmn != 0 || cpus_have_final_cap(ARM64_HAS_HPMN0)); } + +/** + * kvm_pmu_hpmn() - Calculate HPMN field value + * @vcpu: Pointer to struct kvm_vcpu + * + * Calculate the appropriate value to set for MDCR_EL2.HPMN. If + * partitioned, this is the number of counters set for the guest if + * supported, falling back to max_guest_counters if needed. If we are not + * partitioned or can't set the implied HPMN value, fall back to the + * host value. + * + * Return: A valid HPMN value + */ +u8 kvm_pmu_hpmn(struct kvm_vcpu *vcpu) +{ + u8 nr_guest_cntr = vcpu->kvm->arch.nr_pmu_counters; + + if (kvm_vcpu_pmu_is_partitioned(vcpu) + && !vcpu_on_unsupported_cpu(vcpu) + && (cpus_have_final_cap(ARM64_HAS_HPMN0) || nr_guest_cntr > 0)) + return nr_guest_cntr; + + return *host_data_ptr(nr_event_counters); +} diff --git a/arch/arm64/kvm/pmu.c b/arch/arm64/kvm/pmu.c index ee2f0f7e61bcf..8c10ad05661bc 100644 --- a/arch/arm64/kvm/pmu.c +++ b/arch/arm64/kvm/pmu.c @@ -542,6 +542,13 @@ u8 kvm_arm_pmu_get_max_counters(struct kvm *kvm) if (cpus_have_final_cap(ARM64_WORKAROUND_PMUV3_IMPDEF_TRAPS)) return 1; + /* + * If partitioned then we are limited by the max counters in + * the guest partition. + */ + if (kvm_pmu_is_partitioned(arm_pmu)) + return arm_pmu->max_guest_counters; + /* * The arm_pmu->cntr_mask considers the fixed counter(s) as well. * Ignore those and return only the general-purpose counters. diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index c3987e0c01775..6aaeb27642540 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -94,6 +94,9 @@ void kvm_vcpu_pmu_resync_el0(void); bool kvm_pmu_is_partitioned(struct arm_pmu *pmu); +u8 kvm_pmu_guest_num_counters(struct kvm_vcpu *vcpu); +u8 kvm_pmu_hpmn(struct kvm_vcpu *vcpu); + #if !defined(__KVM_NVHE_HYPERVISOR__) bool kvm_vcpu_pmu_is_partitioned(struct kvm_vcpu *vcpu); bool kvm_vcpu_pmu_use_fgt(struct kvm_vcpu *vcpu); @@ -156,6 +159,14 @@ static inline bool kvm_vcpu_pmu_use_fgt(struct kvm_vcpu *vcpu) { return false; } +static inline u8 kvm_pmu_guest_num_counters(struct kvm_vcpu *vcpu) +{ + return 0; +} +static inline u8 kvm_pmu_hpmn(struct kvm_vcpu *vcpu) +{ + return 0; +} static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val) {} static inline void kvm_pmu_set_counter_value_user(struct kvm_vcpu *vcpu, -- 2.54.0.545.g6539524ca2-goog